DATA SHEET www.onsemi.com Low Voltage Single Supply MARKING SPDT Analog Switch DIAGRAMS TSOP6 NLAST4599 A1M DT SUFFIX The NLAST4599 is an advanced high speed CMOS single pole CASE 318G 1 double throw analog switch fabricated with silicon gate CMOS technology. It achieves high speed propagation delays and low ON resistances while maintaining low power dissipation. This switch controls analog and digital voltages that may vary across the full powersupply range (from V to GND). CC SC88/SC70/SOT363 A1M The device has been designed so the ON resistance (R ) is much DF SUFFIX ON CASE 419B lower and more linear over input voltage than R of typical CMOS ON analog switches. 1 The channel select input structure provides protection when voltages between 0 V and 5.5 V are applied, regardless of the supply A1 = Specific Device Code voltage. This input structure helps prevent device destruction caused A = Assembly Location M = Date Code* by supply voltage input/output voltage mismatch, battery backup, = PbFree Package hot insertion, etc. (Note: Microdot may be in either location) Features *Date Code orientation and/or position and underbar may vary depending upon manufacturing location. Select Pin Compatible with TTL Levels Channel Select Input OverVoltage Tolerant to 5.5 V Fast Switching and Propagation Speeds FUNCTION TABLE BreakBeforeMake Circuitry Select ON Channel Low Power Dissipation: I = 2 A (Max) at T = 25C CC A L NC Diode Protection Provided on Channel Select Input H NO Improved Linearity and Lower ON Resistance over Input Voltage Latchup Performance Exceeds 300 mA ESD Performance: HBM > 2000 V MM > 200 V Chip Complexity: 38 FETs ORDERING INFORMATION See detailed ordering and shipping information in the package NLVAST Prefix for Automotive and Other Applications Requiring dimensions section on page 4 of this data sheet. Unique Site and Control Change Requirements AECQ100 Qualified and PPAP Capable These Devices are PbFree, Halogen Free/BFR Free and are RoHS Compliant 1 NO SELECT 6 2 V 5 COM + GND 3 4 NC Figure 1. Pin Assignment CHANNEL SELECT 2 X 0 2 X 1 NO COM NC Figure 2. Logic Symbol Semiconductor Components Industries, LLC, 2006 1 Publication Order Number: September, 2021 Rev. 10 NLAST4599/D U U UNLAST4599 MAXIMUM RATINGS (Note 1) Parameter Symbol Value Unit Positive DC Supply Voltage V 0.5 to +7.0 V CC Analog Input Voltage (V or V ) V 0.5 V V 0.5 V NO COM IS IS CC Digital Select Input Voltage V 0.5 V + 7.0 V IN I DC Current, Into or Out of Any Pin I 50 mA IK Power Dissipation in Still Air SC88 P 200 mW D TSOP6 200 Storage Temperature Range T 65 to +150 C STG Lead Temperature, 1mm from Case for 10 seconds T 260 C L Junction Temperature Under Bias T 150 C J ESD Withstand Voltage Human Body Model (Note 2) V 2000 V ESD Machine Model (Note 3) 200 Charged Device Model (Note 4) N/A Latchup Performance Above V and Below GND at 125C (Note 5) I 300 mA CC LATCHUP Thermal Resistance SC88 333 C/W JA TSOP6 333 Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected. 1. Maximum Ratings are those values beyond which damage to the device may occur. Functional operation should be restricted to the Recommended Operating Conditions. 2. Tested to EIA/JESD22A114A 3. Tested to EIA/JESD22A115A 4. Tested to JESD22C101A 5. Tested to EIA/JESD78 RECOMMENDED OPERATING CONDITIONS Characteristics Symbol Min Max Unit DC Supply Voltage V 2.0 5.5 V CC Digital Select Input Voltage V GND 5.5 V IN Analog Input Voltage (NC, NO, COM) V GND V V IS CC Operating Temperature Range T 55 +125 C A Input Rise or Fall Time t , t ns/V r f SELECT V = 3.3 V + 0.3 V 0 100 CC V = 5.0 V + 0.5 V 0 20 CC Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond the Recommended Operating Ranges limits may affect device reliability. DEVICE JUNCTION TEMPERATURE VERSUS TIME TO 0.1% BOND FAILURES FAILURE RATE OF PLASTIC = CERAMIC UNTIL INTERMETALLICS OCCUR Junction Temperature C Time, Hours Time, Years 80 1,032,200 117.8 90 419,300 47.9 100 178,700 20.4 1 110 79,600 9.4 1 10 100 1000 120 37,000 4.2 TIME, YEARS 130 17,800 2.0 Figure 3. Failure Rate vs. Time Junction Temperature 140 8,900 1.0 www.onsemi.com 2 NORMALIZED FAILURE RATE T = 130C J T = 120C J T = 110C J T = 100C J T = 90C J T = 80C J