NLSF3T125MNR2G ON Semiconductor

NLSF3T125 Quad Bus Buffer with 3State Control Inputs The NLSF3T125 is a high speed CMOS quad bus buffer fabricated with silicon gate CMOS technology. It achieves high speed operation similar to equivalent Bipolar Schottky TTL while maintaining CMOS NLSF3T125 ActiveLow Output Enables 16 1 A1 Y1 15 OE1 5 4 A2 Y2 3 OE2 7 8 Y3 A3 9 OE3 10 12 A4 Y4 13 OE4 Figure 1. Logic Diagram A1 OE1V OE4 CC Exposed Pad (EP) 16 15 14 13 Y1 A4 1 12 NC 2 11 NC OE2 Y4 3 10 A2 9 OE3 4 5 678 Y2 GND Y3 A3 Figure 2. QFN 16 Pinout (Top View) MAXIMUM RATINGS Symbol Parameter Value Units This device contains protection circuitry to guard against damage V DC Supply Voltage 0.5 to +7.0 V CC due to high static voltages or electric V DC Input Voltage 0.5 to +7.0 V in fields. However, precautions must be taken to avoid applications of any V DC Output Voltage V out voltage higher than maximum rated Output in 3State 0.5 to +7.0 voltages to this highimpedance cir- High or Low State 0.5 to V + 0.5 CC cuit. For proper operation, V and in I Input Diode Current 20 mA IK V should be constrained to the out range GND (V or V ) V . in out CC I Output Diode Current (V < GND V > V ) 20 mA OK OUT OUT CC Unused inputs must always be I DC Output Current, per Pin 25 mA tied to an appropriate logic voltage out level (e.g., either GND or V ). CC I DC Supply Current, V and GND Pins 75 mA CC CC Unused outputs must be left open. P Power Dissipation in Still Air mW D QFN Packages 500 T Storage Temperature 65 to +150 C stg Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability.