2-Bit 20 Mb/s Dual-Supply Level Translator NLSX4302E The NLSX4302E is a 2bit configurable dualsupply bidirectional auto sensing translator that does not require a directional control pin. The V I/O and V I/O ports are designed to track two different CC L www.onsemi.com power supply rails, V and V respectively. Both the V and V CC L CC L supply rails are configurable from 1.5 V to 5.5 V. This allows voltage MARKING logic signals on the V side to be translated into lower, higher or L DIAGRAMS equal value voltage logic signals on the V side, and viceversa. CC UQFN8 The NLSX4302E translator uses external pullup resistors on the EM MU SUFFIX I/O lines. The external pullup resistors are used to pull up the I/O 1 CASE 523AS lines to either V or V . The NLSX4302E is an excellent match for L CC 2 opendrain applications such as the I C communication bus. E = Specific Device Code M = Date Code Features V can be Less than, Greater than or Equal to V L CC Wide V Operating Range: 1.5 V to 5.5 V CC LOGIC DIAGRAM Wide V Operating Range: 1.5 V to 5.5 V L V V GND L CC HighSpeed with 20 Mb/s Guaranteed Date Rate EN Low BittoBit Skew Enable Input and I/O Pins are Overvoltage Tolerant (OVT) to 5.5 V I/O V 1 I/O V 1 Non preferential Powerup Sequencing L CC PowerOff Protection Small Space Saving Package: 1.4 mm x 1.2 mm UQFN8 Package I/O V 2 I/O V 2 These Devices are PbFree and are RoHS Compliant L CC Typical Applications 2 I C, SMBus Low Voltage ASIC Level Translation ORDERING INFORMATION Mobile Phones, PDAs, Cameras Device Package Shipping Important Information NLSX4302EBMUTCG UQFN8 3000/Tape & ESD Protection for All Pins (PbFree) Reel Human Body Model (HBM) > 6000 V For information on tape and reel specifications, Machine Model (MM) > 400 V including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specification Brochure, BRD8011/D. Semiconductor Components Industries, LLC, 2012 1 Publication Order Number: August, 2021 Rev. 1 NLSX4302E/DNLSX4302E Figure 1. Block Diagram (1 I/O Line) V L 1 I/O V 1 2 8 V L CC 3 7 I/O V 2 I/O V 1 L CC GND 4 6 I/O V 2 CC 5 EN UQFN8 (Top Through View) Figure 2. Pinout Diagram PIN ASSIGNMENT FUNCTION TABLE Pins Description EN Operating Mode V V Supply Voltage L HiZ CC CC V V Supply Voltage H I/O Buses Connected L L GND Ground EN Output Enable, Referenced to V L I/O V n I/O Port, Referenced to V CC CC I/O V n I/O Port, Referenced to V L L www.onsemi.com 2