NLV74LVX573DTR2G ON Semiconductor

MC74LVX573 Octal D-Type Latch with 3-State Outputs With 5 VTolerant Inputs The MC74LVX573 is an advanced high speed CMOS octal latch MC74LVX573 1 Table 1. PIN NAMES OE Pins Function 11 LE OE Output Enable Input 19 nLE LE Latch Enable Input O0 2 Q D0D7 Data Inputs D0 D O0O7 3State Latch Outputs 18 nLE INPUTS OUTPUTS O1 3 Q D1 D OE LE Dn On OPERATING MODE L H H H Transparent (Latch 17 nLE L H L L Disabled) Read Latch O2 4 Q D2 D L L h H Latched (Latch Enabled) L L l L Read Latch 16 nLE L L X NC Hold Read Latch O3 5 Q D3 H L X Z Hold Disabled Outputs D H H H Z Transparent (Latch H H L Z Disabled) Disabled Outputs 15 nLE O4 6 Q H L h Z Latched (Latch Enabled) D4 D H L l Z Disabled Outputs H = High Voltage Level h = High Voltage Level One Setup Time 14 nLE Prior to the Latch Enable HightoLow Transition L = Low O5 7 Q Voltage Level l = Low Voltage Level One Setup Time Prior to the D5 D Latch Enable HightoLow Transition NC = No Change, State Prior to the Latch Enable HightoLow Transition X = High or Low Voltage Level or Transitions are Acceptable Z = High 13 nLE Impedance State For I Reasons DO NOT FLOAT Inputs. O6 8 CC Q D6 D 12 nLE O7 9 Q D7 D Figure 1. Logic Diagram MAXIMUM RATINGS Symbol Parameter Value Unit V DC Supply Voltage 0.5 to +7.0 V CC V DC Input Voltage 0.5 to +7.0 V in V DC Output Voltage 0.5 to V +0.5 V out CC I Input Diode Current 20 mA IK I Output Diode Current 20 mA OK I DC Output Current, per Pin 25 mA out I DC Supply Current, V and GND Pins 75 mA CC CC P Power Dissipation 180 mW D T Storage Temperature 65 to +150 C stg Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected.