MC74VHCT14A Hex Schmitt Inverter The MC74VHCT14A is an advanced high speed CMOS Schmitt inverter fabricated with silicon gate CMOS technology. It achieves high speed operation similar to equivalent Bipolar Schottky TTL while maintaining CMOS low power dissipation. Pin configuration and function are the same as the www.onsemi.com MC74VHCT04A, but the inputs have hysteresis and, with its Schmitt trigger function, the VHCT14A can be used as a line receiver which MARKING will receive slow input signals. DIAGRAMS The VHCT inputs are compatible with TTL levels. This device can be used as a level converter for interfacing 3.3 V to 5.0 V, because it 14 has full 5.0 V CMOS level output swings. SOIC14 VHCT14AG The VHCT14A input structures provide protection when voltages D SUFFIX AWLYWW CASE 751A between 0 V and 5.5 V are applied, regardless of the supply voltage. 1 The output structures also provide protection when V = 0 V. These 1 CC input and output structures help prevent device destruction caused by 14 supply voltage input/output voltage mismatch, battery backup, hot VHCT insertion, etc. TSSOP14 14A DT SUFFIX The internal circuit is composed of three stages, including a buffer ALYW CASE 948G output which provides high noise immunity and stable output. The 1 inputs tolerate voltages up to 7.0 V, allowing the interface of 5.0 V 1 systems to 3.0 V systems. A = Assembly Location Features WL, L = Wafer Lot Y, YY = Year High Speed: t = 5.5 ns (Typ) at V = 5.0 V PD CC WW, W = Work Week Low Power Dissipation: I = 2.0 A (Max) at T = 25C CC A G or = PbFree Package TTLCompatible Inputs: V = 0.8 V V = 2.0 V (Note: Microdot may be in either location) IL IH Power Down Protection Provided on Inputs FUNCTION TABLE Balanced Propagation Delays Designed for 2.0 V to 5.5 V Operating Range Inputs Outputs Low Noise: V = 0.8 V (Max) OLP A Y Pin and Function Compatible with Other Standard Logic Families L H Chip Complexity: 60 FETs or 15 Equivalent Gates H L NLV Prefix for Automotive and Other Applications Requiring Unique Site and Control Change Requirements AECQ100 ORDERING INFORMATION Qualified and PPAP Capable See detailed ordering and shipping information in the package These Devices are PbFree and are RoHS Compliant dimensions section on page 4 of this data sheet. Semiconductor Components Industries, LLC, 2015 1 Publication Order Number: August, 2017 Rev. 8 MC74VHCT14A/DMC74VHCT14A 1 2 A1 Y1 3 4 A2 Y2 V A6 Y6 A5 Y5 A4 Y4 CC 5 6 14 13 12 11 10 9 8 A3 Y3 Y = A 9 8 A4 Y4 11 10 A5 Y5 1 2 3 4 567 A1 Y1 A2 Y2 A3 Y3 GND 13 12 A6 Y6 Pinout: 14Lead Packages (Top View) Figure 1. Logic Diagram MAXIMUM RATINGS Parameter Symbol Value Unit DC Supply Voltage V 0.5 to +7.0 V CC DC Input Voltage V 0.5 to +7.0 V IN DC Output Voltage Output in HIGH or LOW State (Note 1) V 0.5 to V +0.5 V V OUT CC V = 0 V V 0.5 to 7.0 V CC OUT DC Input Diode Current I 20 mA IK DC Output Diode Current I 20 mA OK DC Output Source/Sink Current I 25 mA O DC Supply Current per Supply Pin I 50 mA CC DC Ground Current per Ground Pin I 50 mA GND Storage Temperature Range T 65 to +150 C STG Lead Temperature, 1 mm from Case for 10 Seconds T 260 C L Junction Temperature under Bias T +150 C J Thermal Resistance SOIC 125 C/W JA TSSOP 170 Power Dissipation in Still Air SOIC P 500 mW D TSSOP 450 ESD Withstand Voltage Human Body Model (Note 2) V >2000 V ESD Machine Model (Note 3) >200 Charged Device Model (Note 4) 2000 Latchup Performance Above V and Below GND at 85C (Note 5) I 300 mA CC Latchup Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected. 1. I absolute maximum rating must be observed. O 2. Tested to EIA/JESD22A114A. 3. Tested to EIA/JESD22A115A. 4. Tested to JESD22C101A. 5. Tested to EIA/JESD78. www.onsemi.com 2