PCA9517A 2 Level-Translating I C-Bus Repeater 2 The PCA9517A is an I Cbus repeater that provides level shifting between low voltage (down to 0.9 V) and higher voltage (2.7 V to 2 5.5 V) for I Cbus or SMBus applications. www.onsemi.com Features MARKING 2 Channel, Bidirectional Buffer Isolates Capacitance and Allows DIAGRAMS 400 pF on Either Side of the Device 8 Voltage Level Translation from 0.9 V to 5.5 V and from 2.7 V to Micro8 9517 5.5 V DM SUFFIX AYW Footprint and Functional Replacement for PCA9515/15A CASE 846A 2 I Cbus and SMBus Compatible 1 Active HIGH Repeater Enable 8 OpenDrain Inputs/Outputs 9517 SOIC8 Lockup Free Operation 8 AYWW CASE 751 Supports Arbitration and Clock Stretching Across the Repeater, and 1 1 Multiple Masters 2 I C and SMBus SCL Clock Frequency up to 1 MHz (The maximum A = Assembly Location L = Wafer Lot system operating frequency may be less than 1 MHz because of the M = Date Code delays added by the repeater.) Y = Year 2 PoweredOff HighImpedance I Cbus Pins W = Work Week = PbFree Package A Side Operating Supply Voltage Range of 0.9 V to 5.5 V (Note: Microdot may be in either location) B Side Operating Supply Voltage Range of 2.7 V to 5.5 V 2 5 V Tolerant I Cbus and Enable Pins Available in: Micro8, SOIC8 ORDERING INFORMATION See detailed ordering and shipping information on page 12 of ESD Performance: 8 kV HBM, 700 V MM, 2000 V CDM this data sheet. These are PbFree Devices Semiconductor Components Industries, LLC, 2014 1 Publication Order Number: May, 2018 Rev. 2 PCA9517A/DPCA9517A General Description PCA9515A, PCA9516A, PCA9517A (port B), or 2 The PCA9517A is an I Cbus repeater that provides level PCA9518. The A side of two or more PCA9517As can be shifting between low voltage (down to 0.9 V) and higher connected together, however, to allow a star topology with 2 voltage (2.7 V to 5.5 V) for I Cbus or SMBus applications. the A side on the common bus, and the A side can be While retaining all the operating modes and features of the connected directly to any other buffer with static or dynamic 2 I Cbus system during the level shifts, it also permits offset voltage. Multiple PCA9517As can be connected in 2 extension of the I Cbus by providing bidirectional series, A side to B side, with no buildup in offset voltage buffering for both the data (SDA) and the clock (SCL) lines, with only timeofflight delays to consider. thus enabling two buses of 400 pF. Using the PCA9517A The PCA9517A drivers are not enabled unless the bus is enables the system designer to isolate two halves of a bus for idle, V is above 0.8 V and V is above 2.5 V. The CC(A) CC(B) both voltage and capacitance. The SDA and SCL pins are EN pin can also be used to turn the drivers on and off under overvoltage tolerant and are highimpedance when the system control. Caution should be observed to only change PCA9517A is unpowered. the state of the enable pin when the bus is idle. The 2.7 V to 5.5 V bus B side drivers behave much like the The output pulldown on the B side internal buffer LOW drivers on the PCA9515A device, while the adjustable is set for approximately 0.5 V, while the input threshold of voltage bus A side drivers drive more current and eliminate the internal buffer is set about 70 mV lower (0.43 V). When the static offset voltage. This results in a LOW on the B side the B side I/O is driven LOW internally, the LOW is not translating into a nearly 0 V LOW on the A side which recognized as a LOW by the input. This prevents a lockup accommodates smaller voltage swings of lower voltage condition from occurring. The output pulldown on the A logic. side drives a hard LOW and the input level is set at The static offset design of the B side PCA9517A I/O 0.3 V to accommodate the need for a lower LOW level CC(A) drivers prevents them from being connected to another in systems where the low voltage side supply voltage is as device that has a rise time accelerator including the low as 0.9 V. PCA9510, PCA9511, PCA9512, PCA9513, PCA9514, BLOCK DIAGRAM Figure 1. Block Diagram of PCA9517A www.onsemi.com 2