PCA9617A Level-Translating Fm+ 2 I C-Bus Repeater 2 The PCA9617A is an I Cbus repeater that provides level shifting between low voltage (0.8 V to 5.5 V) and higher voltage (2.2 V to 2 5.5 V) for FastMode Plus (Fm+) I Cbus or SMBus applications. PCA9617A General Description incremented offset of other bus buffers. Port A of two or 2 The PCA9617A is an I Cbus repeater that provides level more PCA9617As can be connected together, however, to shifting between low voltage (0.8 V to 5.5 V) and higher allow a star topography with port A on the common bus, and 2 voltage (2.2 V to 5.5 V) for FastMode Plus (Fm+) I Cbus port A can be connected directly to any other buffer with or SMBus applications. While retaining all the operating static or incremented offset outputs. Multiple PCA9617As 2 modes and features of the I Cbus system during the level can be connected in series, port A to port B, with no buildup 2 shifts, it also permits extension of the I Cbus by providing in offset voltage with only time of flight delays to consider. bidirectional buffering for both the data (SDA) and the clock The PCA9617A drivers are not enabled unless V is CC(A) (SCL) lines, thus enabling two buses of 540 pF at 1 MHz or above 0.8 V and V is above 2.2 V. The EN pin is CC(B) up to 4000 pF at lower speeds. Using the PCA9617A enables referenced to V and can also be used to turn the drivers CC(B) the system designer to isolate two halves of a bus for both on and off under system control. Caution should be observed voltage and capacitance. The SDA and SCL pins are to only change the state of the enable pin when the bus is idle. overvoltage tolerant and are highimpedance when the The output pulldown on the port B internal buffer LOW PCA9617A is unpowered. is set for approximately 0.55 V, while the input threshold of The 2.2 V to 5.5 V bus port B drivers have the static level the internal buffer is set about 90 mV lower (0.45 V). When offset, while the adjustable voltage bus port A drivers the port B I/O is driven LOW internally, the LOW is not eliminate the static offset voltage. This results in a LOW on recognized as a LOW by the input. This prevents a latching the port B translating into a nearly 0 V LOW on the port A condition from occurring. The output pulldown on port A which accommodates the smaller voltage swings of lower drives a hard LOW and the input level is set at 0.35V CC(A) voltage logic. to accommodate the need for a lower LOW level in systems The static offset design of the port B PCA9617A I/O where the low voltage side supply voltage is as low as 0.8 V. drivers prevents them from being connected to the static or BLOCK DIAGRAM Figure 1. Block Diagram of PCA9617A