MC10E111, MC100E111 5 V ECL 1:9 Differential Clock Driver Description The MC10E/100E111 is a low skew 1-to-9 differential driver, designed with clock distribution in mind. It accepts one signal input, www.onsemi.com which can be either differential or else single-ended if the V output BB is used. The signal is fanned out to 9 identical differential outputs. An enable input is also provided. A HIGH disables the device by forcing all Q outputs LOW and all Q outputs HIGH. The device is specifically designed, modeled and produced with low skew as the key goal. Optimal design and layout serve to minimize gate to gate skew within-device, and empirical modeling is used to PLCC28 determine process control limits that ensure consistent t FN SUFFIX pd CASE 77602 distributions from lot to lot. The net result is a dependable, guaranteed low skew device. The lowest TPD delay time results from terminating only one output pair, and the greatest TPD delay time results from terminating all the MARKING DIAGRAM* output pairs. This shift is about 1020 pS in TPD. The skew between 1 any two output pairs within a device is typically about 25 nS. If other output pairs are not terminated, the lowest TPD delay time results from both output pairs and the skew is typically 25 nS. When all MCxxxE111G outputs are terminated, the greatest TPD (delay time) occurs and all AWLYYWW outputs display about the same 1020 pS increase in TPD, so the relative skew between any two output pairs remains about 25 nS. The V pin, an internally generated voltage supply, is available to BB xxx = 10 or 100 this device only. For single-ended input conditions, the unused A = Assembly Location differential input is connected to V as a switching reference voltage. BB WL = Wafer Lot V may also rebias AC coupled inputs. When used, decouple V BB BB YY = Year and V via a 0.01 F capacitor and limit current sourcing or sinking CC WW = Work Week G = Pb-Free Package to 0.5 mA. When not used, V should be left open. BB The 100 Series contains temperature compensation. *For additional marking information, refer to Application Note AND8002/D. Features Guaranteed Skew Spec ORDERING INFORMATION Differential Design V Output Device Package Shipping BB PECL Mode Operating Range: V = 4.2 V to 5.7 V MC10E111FNG PLCC28 37 Units/Tube CC (Pb-Free) with V = 0 V EE MC10E111FNR2G PLCC28 500 Tape & Reel NECL Mode Operating Range: V = 0 V CC (Pb-Free) with V = 4.2 V to 5.7 V EE 37 Units/Tube MC100E111FNG PLCC28 Internal Input 50 K Pulldown Resistors (Pb-Free) ESD Protection: > 3 kV Human Body Model MC100E111FNR2G PLCC28 500 Tape & Reel Meets or Exceeds JEDEC Standard EIA/JESD78 IC Latchup Test (Pb-Free) Moisture Sensitivity: Level 3 (Pb-Free) For information on tape and reel specifications, in- (For Additional Information, see Application Note AND8003/D) cluding part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Flammability Rating: UL 94 V0 0.125 in, Brochure, BRD8011/D. Oxygen Index: 28 to 34 Transistor Count = 178 Devices These Devices are Pb-Free, Halogen Free and are RoHS Compliant Semiconductor Components Industries, LLC, 2016 1 Publication Order Number: July, 2016 Rev. 17 MC10E111/DMC10E111, MC100E111 Q Q Q V Q Q Q 0 0 1 CCO 1 2 2 Table 1. PIN DESCRIPTION 25 24 23 22 21 20 19 PIN FUNCTION V Q 26 18 EE 3 IN, IN ECL Differential Input Pair EN ECL Enable Q Q , Q Q , Q ECL Differential Outputs EN 27 17 0 0 8 8 3 V Reference Voltage Output BB V , V Positive Supply CC CCO Q IN 28 16 4 V Negative Supply EE NC No Connect Pinout: 28-Lead PLCC V 15 V CC 1 CCO (Top View) IN Q 2 14 4 3 13 Q V 5 BB NC 4 12 Q 5 56 7 8 9 10 11 Q Q Q V Q Q Q 8 8 7 CCO 7 6 6 * All V and V pins are tied together on the die. CC CCO Warning: All V , V , and V pins must be exter- CC CCO EE nally connected to Power Supply to guarantee proper operation. Figure 1. 28-Lead Pinout Q 0 Q 0 Q 1 Q 1 Q 2 Q 2 Q 3 Q 3 IN Q 4 Q IN 4 Q 5 EN Q 5 Q 6 Q 6 Q 7 Q 7 Q 8 Q 8 V BB Figure 2. Logic Symbol www.onsemi.com 2