Doc No. TT4-EA-12566
Revision. 2
Product Standards
MOS FET
FK6K02010L
FK6K02010L
Silicon N-channel MOS FET
Unit : mm
2.0
For switching
0.2 0.13
6 5 4
Features
Low drain-source On-state Resistance:RDS(on)typ. = 13 m VGS = 4.5 V)
Low drive voltage: 2.5 V drive
Halogen-free / RoHS compliant
(EU RoHS / UL-94 V-0 / MSL : Level 1 compliant)
12 3
0.7
Marking Symbol :
TA
(0.65)(0.65)
1.3
Packaging
Embossed type (Thermo-compression sealing): 3 000 pcs / reel (standard)
1. Drain 4. Source
2. Drain 5. Drain
3. Gate 6. Drain
Panasonic WSMini6-F1-B
Absolute Maximum Ratings Ta = 25 C
JEITA SC-113DA
Parameter Symbol Rating Unit
Drain-source surrender voltage VDSS 20 V Code
Gate-source surrender voltage VGSS 10 V
Drain current ID 4.5 A
Internal Connection
*1
IDp 18 A
Peak drain current
*2
PD 700 mW
Power dissipation
Channel temperature Tch 150 C
Operating ambient temperature Topr -40 to + 85 C
Storage temperature Tstg -55 to +150
C
Note) *1 t = 10 s, Duty Cycle < 1%
*2 Measuring on Glass epoxy board (25.4 25.4 t0.8 mm)
2
coated with copper foil, which has more than 300 mm
Absolute maximum rating without heat sink for PD is 150 mW.
Pin Name
1. Drain 4. Source
2. Drain 5. Drain
3. Gate 6. Drain
Page 1of 6
Established : 2010-06-07
Revised : 2013-07-01
1.7
2.1Doc No. TT4-EA-12566
Revision. 2
Product Standards
MOS FET
FK6K02010L
Electrical Characteristics Ta = 25 C 3C
Parameter Symbol Conditions Min Typ Max Unit
Drain-source surrender voltage VDSS ID = 1 mA, VGS = 0 20 V
Drain-source cutoff current IDSS VDS = 20 V, VGS = 0 1.0 A
Gate-source cutoff current IGSS VGS = 8 V, VDS = 0 10 A
Gate threshold voltage Vth ID = 1.0 mA, VDS = 10.0 V 0.4 0.85 1.3 V
RDS(ON)1 ID = 2.0 A, VGS = 4.5 V 13 17.5
Drain-source ON resistance m
RDS(ON)2
ID = 1.0 A, VGS = 2.5 V 16 28
Forward transfer admittance |Yfs| ID = 1.0 A, VDS =10 V 3.0 S
Short-circuit input capacitance (Common source) Ciss 1 730 pF
Short-circuit output capacitance (Common source)
Coss VDS = 10 V, VGS = 0, f = 1 MHz 155 pF
Reverse transfer capacitance (Common source) Crss 150 pF
*1
td(on) 19 ns
Turn-on delay time
VDD = 10 V
*1
tr
Rise time 30 ns
VGS = 0 to 4 V
*1
td(off) 150 ns
Turn-off delay time
ID=1.0A
*1
tf 75 ns
Fall time
Note)
1. Measuring methods are based on JAPANESE INDUSTRIAL STANDARD JIS C 7030 Measuring methods for transistors.
2. *1 Measurement circuit for Turn-on Delay Time/Rise Time/Turn-off Delay Time/Fall Time
Page 2of 6
Established : 2010-06-07
Revised : 2013-07-01