Document Type: Data Sheet ICS1893AF Document Stage: Release 3.3-V 10Base-T/100Base-TX Integrated PHYceiver General Features The ICS1893AF is a lower cost, re-packaged version of the Single 3.3V power supply ICS1893Y-10. The ICS1893AF is a fully integrated, Physical Supports category 5 cables with attenuation in excess of 24dB at 100 MHz. Layer device (PHY) that is compliant with both the 10Base-T DSP-based baseline wander correction to virtually and 100Base-TX CSMA/CD Ethernet Standard, ISO/IEC eliminate killer packets 8802-3. The ICS1893AF uses the same proven silicon as Low-power, 0.35-micron CMOS (typically 400 mW) the ICS1893Y-10 but offers a lower cost solution by using a Single-chip, fully integrated PHY provides PCS, PMA, lower cost 300 mil. 48-lead SSOP package. PMD, and AUTONEG sublayers of IEEE standard 10Base-T and 100Base-TX IEEE 802.3 compliant The ICS1893AF uses the same twisted-pair transmit and Clock or crystal supported receive circuits as the ICS1893Y-10, and the same Media Independent Interface (MII) supported recommended board layout techniques apply to the Managed or Unmanaged Applications ICS1893AF. 10M or 100M Half and Full Duplex Modes The ICS1893AF is intended for Node applications using the Auto-Negotiation with Parallel detection for Legacy standard MII interface to the MAC. products Fully integrated, DSP-based PMD includes: All differences in the ICS1893AF / ICS1893Y-10 Feature Set Adaptive equalization and baseline wander correction are listed in the Comparison Table on page 14. Transmit wave shaping and stream cipher scrambler MLT-3 encoder and NRZ/NRZI encoder Loopback mode for Diagnostic Functions Small footprint 48-pin 300 mil SSOP package. Available in Industrial Temperature and Lead Free packaging. ICS1893AF Block Diagram 100Base-T PCS PMA TP PMD 10/100 MII Framer Clock Recovery MLT-3 Twisted- Interface Integrated CRS/COL Link Monitor Stream Cipher MAC Detection Signal Detection Adaptive Equalizer Pair MUX Switch Interface Parallel to Serial Error Detection Baseline Wander Interface to 4B/5B Correction Magnetics Modules and 10Base-T RJ45 Connector MII Low-Jitter Auto- Configuration Extended MII Serial Clock Negotiation and Status Register Management Synthesizer Set Interface Clock Power LEDs and PHY Address ICS1893AF, Rev. F 05/13/10 ICS reserves the right to make changes in the device data identified in Octobe this publication without further notice. ICS advises its customers to obtain the latest version of all device data to verify that any information being relied upon by the customer is current and accurate.ICS1893AF Data Sheet - Release Table of Contents Table of Contents Section Title Page Revision History ............................................................................................................................. 9 Chapter 1 Abbreviations and Acronyms .........................................................................................10 Chapter 2 Conventions and Nomenclature.....................................................................................12 Chapter 3 Typical ICS1893AF Applications.....................................................................................14 3.1 ICS1893AF / ICS1893Y-10 Pin Differences ...........................................................14 3.2 ICS1893AF / ICS1893Y-10 Shared Features.........................................................15 Chapter 4 Overview of the ICS1893AF.............................................................................................16 4.1 100Base-TX Operation ..........................................................................................17 4.2 10Base-T Operation ...............................................................................................17 Chapter 5 Operating Modes Overview.............................................................................................18 5.1 Reset Operations ...................................................................................................19 5.1.1 General Reset Operations .....................................................................................19 5.1.2 Specific Reset Operations .....................................................................................20 5.2 Power-Down Operations ........................................................................................21 5.3 Automatic Power-Saving Operations .....................................................................22 5.4 Auto-Negotiation Operations ..................................................................................22 5.5 100Base-TX Operations ........................................................................................23 5.6 10Base-T Operations .............................................................................................23 5.7 Half-Duplex and Full-Duplex Operations ...............................................................23 Chapter 6 Interface Overviews..........................................................................................................24 6.1 MII Data Interface ..................................................................................................25 6.2 Serial Management Interface .................................................................................26 6.3 Twisted-Pair Interface ............................................................................................26 6.3.1 Twisted-Pair Transmitter Interface .........................................................................27 6.3.2 Twisted-Pair Receiver Interface .............................................................................28 6.4 Clock Reference Interface .....................................................................................29 6.5 Status Interface ......................................................................................................31 Chapter 7 Functional Blocks.............................................................................................................33 7.1 Functional Block: Media Independent Interface .....................................................34 7.2 Functional Block: Auto-Negotiation ........................................................................35 7.2.1 Auto-Negotiation General Process ........................................................................36 7.2.2 Auto-Negotiation: Parallel Detection ......................................................................37 7.2.3 Auto-Negotiation: Remote Fault Signaling .............................................................37 7.2.4 Auto-Negotiation: Reset and Restart .....................................................................38 7.2.5 Auto-Negotiation: Progress Monitor .......................................................................38 ICS1893AF, Rev D 10/26/04 October, 2004 Copyright 2004, Integrated Circuit Systems, Inc. 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