ICS2510C 3.3V Phase-Lock Loop Clock Driver General Description Features The ICS2510C is a high performance, low skew, low jitter Meets or exceeds PC133 registered DIMM clock driver. It uses a phase lock loop (PLL) technology to specification1.1 align, in both phase and frequency, the CLKIN signal with Spread Spectrum Clock Compatible the CLKOUT signal. It is specifically designed for use with Distributes one clock input to one bank of ten outputs synchronous SDRAMs. The ICS2510C operates at 3.3V VCC and drives up to ten clock loads. Operating frequency 25MHz to 175MHz One bank of ten outputs provide low-skew, low-jitter External feedback input (FBIN) terminal is used to copies of CLKIN. Output signal duty cycles are adjusted synchrionize the outputs to the clock input to 50 percent, independent of the duty cycle at CLKIN. No external RC network required Outputs can be enabled or disabled via control (OE) inputs. When the OE inputs are high, the outputs align in Operates at 3.3V Vcc phase and frequency with CLKIN when the OE inputs are Plastic 24-pin 173mil TSSOP package low, the outputs are disabled to the logic low state. The ICS2510C does not require external RC filter components. The loop filter for the PLL is included on-chip, minimizing component count, board space, and cost. The test mode shuts off the PLL and connects the input directly to the output buffer. This test mode, the ICS2510C can be use as low skew fanout clock buffer device. The ICS2510C comes in 24 pin 173mil Thin Shrink Small- Outline package (TSSOP) package. Block Diagram Pin Configuration FBOUT AGND 1 24 CLKIN CLK0 VCC 2 23 AVCC CLK1 CLK0 3 22 VCC CLK1 4 21 CLK9 CLK2 FBIN CLK2 5 20 CLK8 PLL CLK3 GND 6 19 GND CLKIN GND 7 18 GND CLK4 CLK3 8 17 CLK7 AVCC CLK5 CLK4 9 16 CLK6 VCC 10 15 CLK5 CLK6 OE 11 14 VCC CLK7 FBOUT 12 13 FBIN CLK8 24 Pin TSSOP CLK9 4.40 mm. Body, 0.65 mm. pitch OE 0010G09/22/09ICS2510C Pin Descriptions PIN NUMBER PIN NAME TYPE DESCRIPTION 1 AGND PWR Analog Ground 2, 10, 14 VCC PWR Power Supply (3.3V) 3 CLK0 OUT Buffered clock output. 4 CLK1 OUT Buffered clock output. 5 CLK2 OUT Buffered clock output. 6, 7, 18, 19 GND PWR Ground 8 CLK3 OUT Buffered clock output. 9 CLK4 OUT Buffered clock output. Output enable (has internal pull up). When high, normal operation. 1 11 IN OE When low, clock outputs are disabled to a logic low state. 12 FBOUT OUT Feedback output 13 FBIN IN Feedback input 15 CLK5 OUT Buffered clock output. 16 CLK6 OUT Buffered clock output. 17 CLK7 OUT Buffered clock output. 20 CLK8 OUT Buffered clock output. 21 CLK9 OUT Buffered clock output. 22 VCC PWR Power Supply (3.3V) digital supply. Analog power supply (3.3V). When input is ground PLL is off and 23 AVCC IN bypassed. Clock input 24 CLKIN IN Note: 1. Weak pull-ups on these inputs Functionality INPUTS OUTPUTS PLL OE AVCC CLK (9:0) FBOUT Source Shutdown 03.33 0 Driven PLL N 13.33 Driven Driven PLL N Buffer Mode 00 0 Driven CLKIN Y Driven 1 0 Driven CLKIN Y Test mode: When AVCC is 0, shuts off the PLL and connects the input directly to the output buffers 0010G09/22/09 2