Field Programmable SS VersaClock ICS251 Synthesizer DATASHEET Description Features The ICS251 is a low cost, single-output, field programmable 8-pin SOIC package clock synthesizer. The ICS251 can generate an output Four addressable registers frequency from 314kHz to 200MHz and may employ Spread Input crystal frequency of 5 to 27MHz Spectrum techniques to reduce system electro-magnetic interference (EMI). Clock input frequency of 3 to 150MHz Output clock frequencies up to 200MHz Using IDTs VersaClock software to configure the PLL and output, the ICS251 contains a One-Time Programmable Configurable spread spectrum modulation (OTP) ROM to allow field programmability. Programming Operating voltage of 3.3V features include 4 selectable configuration registers. Replaces multiple crystals and oscillators The device employs Phase-Locked Loop (PLL) techniques to Controllable output drive levels run from a standard fundamental mode, inexpensive crystal, or clock. It can replace multiple crystals and oscillators, Advanced, low-power CMOS process saving board space and cost. RoHS compliant packaging The device also has a power-down feature that tri-states the clock outputs and turns off the PLLs when the PDTS pin is taken low. The ICS251 is also available in factory programmed custom versions for high-volume applications. Block Diagram VDD OTP ROM 2 with PLL S1:0 Divider Values PLL Clock Synthesis, Spread Spectrum and CLK Crystal or Control Circuitry clock input X1/ICLK Crystal Oscillator X2 External capacitors are GND required with a crystal input. PDTS (output and PLL) ICS251 OCTOBER 10, 2017 1 2017 Integrated Device Technology, Inc.ICS251 DATASHEET Pin Assignment Output Clock Selection Table S1 S0 CLK (MHz) Spread S0 1 8 PDTS Percentage 0 0 User Configurable User Configurable VDD 2 7 GND 0 1 User Configurable User Configurable X1/ICLK 3 6 S1 1 0 User Configurable User Configurable X2 4 5 CLK 1 1 User Configurable User Configurable 8-pin (150 mil) SOIC Pin Descriptions Pin Pin Pin Pin Description Number Name Type 1 S0 Input Select pin 0 for frequency selection on CLK. Internal pull-up resistor. 2 VDD Power Connect to +3.3 V. 3 X1/ICLK XI Connect this pin to a crystal or external clock input. 4 X2 XO Connect this pin to a crystal, or float for clock input. 5 CLK Output Clock output. Weak internal pull-down when tri-state. 6 S1 Input Select pin 1 for frequency selection on CLK. Internal pull-up resistor. 7 GND Power Connect this to ground. Powers down entire chip. Tri-states CLK outputs when low. No internal pull-up resistor. The pin must 8PDTS Input be tied either directly or through the external resistor to VDD or GND. External resistor value must be less than 15kOhm. External Components The ICS251 requires a minimum number of external capacitance. Because load capacitance can only be components for proper operation. increased in this trimming process, it is important to keep stray capacitance to a minimum by using very short PCB traces (and no vias) been the crystal and device. Crystal capacitors Series Termination Resistor must be connected from each of the pins X1 and X2 to ground. Clock output traces over one inch should use series termination. To series terminate a 50 trace (a commonly The value (in pF) of these crystal caps should equal (C -6pF) L used trace impedance), place a 33 resistor in series with the 2. In this equation, C = crystal load capacitance in pF. L clock line, as close to the clock output pin as possible. The Example: For a crystal with a 16pF load capacitance, each nominal impedance of the clock output is 20. crystal capacitor would be 20pF (16-6) x 2 = 20. Decoupling Capacitor As with any high-performance mixed-signal IC, the ICS251 must be isolated from system power supply noise to perform optimally. A decoupling capacitor of 0.01F must be connected between VDD and the PCB ground plane. Crystal Load Capacitors The device crystal connections should include pads for small capacitors from X1 to ground and from X2 to ground. These capacitors are used to adjust the stray capacitance of the board to match the nominally required crystal load FIELD PROGRAMMABLE SS VERSACLOCK SYNTHESIZER 2 OCTOBER 10, 2017