DATASHEET FIELD PROGRAMMABLE DUAL OUTPUT SS VERSACLOCK SYNTHESIZER ICS252 Description Features The ICS252 is a low cost, dual-output, field programmable 8-pin SOIC package Pb-free, RoHS compliant clock synthesizer. The ICS252 can generate two output Two addressable registers frequencies from 314 kHz to 200 MHz using up to two Input crystal frequency of 5 to 27 MHz independently configurable PLLs. The outputs may employ Clock input frequency of 3 to 150 MHz Spread Spectrum techniques to reduce system electro-magnetic interference (EMI). Output clock frequencies up to 200 MHz Configurable Spread Spectrum Modulation Using IDTs VersaClock software to configure the PLL and output, the ICS252 contains a One-Time Programmable Operating voltage of 3.3 V (OTP) ROM to allow field programmability. Programming Replaces multiple crystals and oscillators features include 2 selectable configuration registers. Controllable output drive levels The device employs Phase-Locked Loop (PLL) techniques Advanced, low-power CMOS process to run from a standard fundamental mode, inexpensive crystal, or clock. It can replace multiple crystals and oscillators, saving board space and cost. The device also has a power-down feature that tri-states the clock outputs and turns off the PLLs when the PDTS pin is taken low. The ICS252 is also available in factory programmed custom versions for high-volume applications. Block Diagram VDD OTP PLL1 SEL Divide ROM Logic with CLK1 PLL and Output Values PLL2 Enable CLK2 X1 Control Crystal Crystal Oscillator X2 GND External capacitors are required. PDTS IDT FIELD PROGRAMMABLE DUAL OUTPUT SS VERSACLOCK SYNTHESIZER 1 ICS252 REV K 030212ICS252 FIELD PROGRAMMABLE DUAL OUTPUT SS VERSACLOCK SYNTHESIZER EPROM CLOCK SYNTHESIZER Pin Assignment Output Clock Selection Table SEL CLK1 (MHz) CLK2 (MHz) Spread SEL 1 8 PD TS Percentage VD D 2 7 GN D 0 User User User Configurable Configurable Configurable X1 /IC L K 3 6 CLK2 1User User User Configurable Configurable Configurable X2 4 5 CLK1 8-pin (150 mil) SOIC Pin Descriptions Pin Pin Pin Pin Description Number Name Type 1 SEL Input Select pin for frequency selection on CLK1 and CLK2. Internal pull-up resistor. 2 VDD Power Connect to +3.3 V. 3 X1/ICLK XI Connect this pin to a crystal or external clock input. 4 X2 XO Connect this pin to a crystal, or float for clock input. 5 CLK1 Output Clock1 output. Weak internal pull-down, low when power down. 6 CLK2 Output Clock2 output. Weak internal pull-down, low when power down. 7 GND Power Connect this to ground. Powers down entire chip. Tri-states CLK outputs when low. No internal pull-up 8PDTS Input resistor. The pin must be tied either directly or through the external resistor to VDD ro GND. External resistor value must be less than 15kOhm. External Components The ICS252 requires a minimum number of external Crystal Load Capacitors components for proper operation. The device crystal connections should include pads for small capacitors from X1 to ground and from X2 to ground. Series Termination Resistor These capacitors are used to adjust the stray capacitance Clock output traces over one inch should use series of the board to match the nominally required crystal load termination. To series terminate a 50 trace (a commonly capacitance. Because load capacitance can only be used trace impedance), place a 33 resistor in series with increased in this trimming process, it is important to keep the clock line, as close to the clock output pin as possible. stray capacitance to a minimum by using very short PCB The nominal impedance of the clock output is 20. traces (and no vias) between the crystal and device. Crystal capacitors must be connected from each of the pins X1 and Decoupling Capacitor X2 to ground. As with any high-performance mixed-signal IC, the ICS252 The value (in pF) of these crystal caps should equal (C -6 L must be isolated from system power supply noise to perform pF)*2. In this equation, C = crystal load capacitance in pF. L optimally. Example: For a crystal with a 16 pF load capacitance, each crystal capacitor would be 20 pF (16-6) x 2 = 20 . A decoupling capacitor of 0.01F must be connected between VDD and the PCB ground plane. IDT FIELD PROGRAMMABLE DUAL OUTPUT SS VERSACLOCK SYNTHESIZER 2 ICS252 REV K 030212