345RIPLF Renesas

DATASHEET TRIPLE PLL FIELD PROGRAMMABLE SS VERSACLOCK SYNTHESIZER ICS345 Description Features The ICS345 field programmable clock synthesizer Packaged as 20-pin SSOP (QSOP) (Pb-free) generates up to nine high-quality, high-frequency clock Spread spectrum capability outputs including multiple reference clocks from a Eight addressable registers low-frequency crystal or clock input. It is designed to Replaces multiple crystals and oscillators replace crystals and crystal oscillators in most electronic Output frequencies up to 200 MHz at 3.3 V systems. Input crystal frequency of 5 to 27 MHz TM Using IDTs VersaClock software to configure PLLs and Input clock frequency of 2 to 50 MHz outputs, the ICS345 contains a One-Time Programmable Up to nine reference outputs (OTP) ROM to allow field programmability. Programming Up to two sets of four low-skew outputs features include eight selectable configuration registers, up to two sets of four low-skew outputs, and optional Spread Operating voltages of 3.3 V Spectrum outputs. Advanced, low-power CMOS process Using Phase-Locked Loop (PLL) techniques, the device For one output clock, use the ICS341. For two output clocks, see the ICS342. For three output clocks, see the runs from a standard fundamental mode, inexpensive ICS343. For more than three outputs, see the ICS348. crystal, or clock. It can replace multiple crystals and oscillators, saving board space and cost. The ICS345 is also available in factory programmed custom versions for high-volume applications. Block Diagram 3 VDD PLL1 with CLK1 3 OTP Spread S2:S0 CLK2 ROM Spectrum with CLK3 PLL Divide Values CLK4 Logic PLL2 and CLK5 Output CLK6 Enable Crystal or Control CLK7 clock input PLL3 X1/ICLK CLK8 Crystal CLK9 Oscillator X2 GND 2 External capacitors are required with a crystal input. PDTS IDT TRIPLE PLL FIELD PROGRAMMABLE SS VERSACLOCK SYNTHESIZER 1 ICS345 REV P 090613ICS345 TRIPLE PLL FIELD PROGRAMMABLE SS VERSACLOCK SYNTHESIZER EPROM CLOCK SYNTHESIZER Pin Assignment X1/ICLK 1 20 X2 S0 2 19 VDD S1 3 18 PDTS CLK9 4 17 S2 VDD VDD 5 16 GND 6 15 GND CLK1 7 14 CLK5 CLK2 8 13 CLK6 CLK3 9 CLK7 12 CLK4 10 CLK8 11 20-pin (150 mil) SSOP (QSOP) Pin Descriptions Pin Pin Pin Pin Description Number Name Type 1 X1/ICLK XI Crystal input. Connect this pin to a crystal or external input clock. 2 S0 Input Select pin 0. Internal pull-up resistor. 3 S1 Input Select pin 1. Internal pull-up resistor. 4 CLK9 Output Output clock 9. Weak internal pull-down when tri-state. Connect to +3.3 V. 5VDD Power 6 GND Power Connect to ground. 7 CLK1 Output Output clock 1. Weak internal pull-down when tri-state. 8 CLK2 Output Output clock 2. Weak internal pull-down when tri-state. 9 CLK3 Output Output clock 3. Weak internal pull-down when tri-state. 10 CLK4 Output Output clock 4. Weak internal pull-down when tri-state. 11 CLK8 Output Output clock 8. Weak internal pull-down when tri-state. 12 CLK7 Output Output clock 7. Weak internal pull-down when tri-state. 13 CLK6 Output Output clock 6. Weak internal pull-down when tri-state. 14 CLK5 Output Output clock 5. Weak internal pull-down when tri-state. 15 GND Power Connect to ground. Connect to +3.3 V. 16 VDD Power 17 S2 Input Select pin 2. Internal pull-up resisitor. Power-down tri-state. Powers down entire chip and tri-states clock outputs 18 PDTS Input when low. Internal pull-up resisitor. Connect to +3.3 V. 19 VDD Power 20 X2 XO Crystal Output. Connect this pin to a crystal. Float for clock input. IDT TRIPLE PLL FIELD PROGRAMMABLE SS VERSACLOCK SYNTHESIZER 2 ICS345 REV P 090613