508MLF Renesas

DATASHEET PECL TO CMOS CONVERTER ICS508 Description Features The ICS508 is the most cost effective way to generate Packaged in 8 pin SOIC (Pb-free) or die a high quality, high frequency CMOS clock output from Separate VDD supplies allow voltage translation a PECL clock input. Clock frequency of 0 - 250 MHz The ICS508 has separate VDD supplies for the PECL Duty cycle of 45/55 input buffer and the output buffer, allowing different Operating voltages of 2.375 to 5.5V voltages to be used. For example, the input clock could use a 3.3 V supply while the output operates from 2.5V. Tri-state output for board level testing The device has an Output Enable pin that tri-states the 24mA output drive capability clock output when the OE pin is taken low. Industrial temperature version available TM The ICS508 is a member of IDTs ClockBlocks Advanced, low power, sub-micron CMOS process family. Block Diagram VDDP VDDC PECLIN Output CLK Buffer PECLIN OE GND GND IDT / ICS PECL TO CMOS CONVERTER 1 ICS508 REV H 051310ICS508 PECL TO CMOS CONVERTER PECL TO CMOS TRANSLATOR Pin Assignment VDDP 1 8 VDDC PECLIN 2 7 CLK PECLIN 3 6 GND GND 4 5 OE 8 Pin (150 mil) SOIC Pin Descriptions Pin Pin Pin Pin Description Number Name Type 1 VDDP Output Connect to 3.3V or 5V. Supplies PECL input buffer. 2PECLIN Input Complementary PECL clock input. 3 PECLIN Input PECL clock input. 4 GND Power Connect to ground. 5 OE Input Output enable. Tri-states CLK output when low. Internal pull-up to VDDC. 6 GND Power Connect to ground. 7 CLK Output Clock output. 8 VDDC Power Connect to 2.5 V, or 3.3 V, or 5 V. Supplies output buffer and OE pin. External Components The ICS508 requires two 0.01F decoupling capacitors to be connected between VDDP and GND and between VDDC and GND. They must be connected close to the ICS508 to minimize lead inductance. A 33 series terminating resistor can be used next to the CLK pin. IDT / ICS PECL TO CMOS CONVERTER 2 ICS508 REV H 051310