70261S15PF Renesas

HIGH-SPEED 70261S/L 16K x 16 DUAL-PORT STATIC RAM WITH INTERRUPT Features IDT70261 easily expands data bus width to 32 bits or more True Dual-Ported memory cells which allow simultaneous using the Master/Slave select when cascading more than access of the same memory location one device High-speed access M/S = H for BUSY output flag on Master, Commercial: 15/55ns (max.) M/S = L for BUSY input on Slave Industrial 20ns (max.) Busy and Interrupt Flags Low-power operation On-chip port arbitration logic IDT70261S Full on-chip hardware support of semaphore signaling Active: 750mW (typ.) between ports Standby: 5mW (typ.) Fully asynchronous operation from either port IDT70261L TTL-compatible, single 5V (10%) power supply Active: 750mW (typ.) Available in 100-pin Thin Quad Flatpack Standby: 1mW (typ.) O O Industrial temperature range (-40 C to +85 C) is available Separate upper-byte and lower-byte control for multiplexed for selected speeds bus compatibility Green parts available. See ordering information Functional Block Diagram R/WL R/WR UBR UBL LBL LBR CEL CER OER OEL I/O8L-I/O15L I/O8R-I/O15R I/O I/O Control Control I/O0L-I/O7L I/O0R-I/O7R (1,2) (1,2) BUSYL BUSYR A13L A13R Address MEMORY Address Decoder ARRAY Decoder A0L A0R 14 14 ARBITRATION CER CEL INTERRUPT OER SEMAPHORE OEL R/WR R/WL LOGIC SEMR SEML (2) (2) INTR INTL M/S 3039 drw 01 NOTES: 1. (MASTER): BUSY is output (SLAVE): BUSY is input. 2. BUSY and INT outputs are non-tri-stated push-pull. JULY 2019 1 DSC 3039/1370261S/L High-Speed 16K x 16 Dual-Port Static RAM with Interrupt Industrial and Commercial Temperature Ranges DescriptionDescription DescriptionDescriptionDescription This device provides two independent ports with separate control, address, and I/O pins that permit independent, asynchronous access for The IDT70261 is a high-speed 16K x 16 Dual-Port Static RAM. The reads or writes to any location in memory. An automatic power down IDT70261 is designed to be used as a stand-alone Dual-Port RAM or as feature controlled by CE permits the on-chip circuitry of each port to enter a combination MASTER/SLAVE Dual-Port RAM for 32-bit-or-more word a very low standby power mode. systems. Using the IDT MASTER/SLAVE Dual-Port RAM approach in 32- Fabricated using CMOS high-performance technology, these de- bit or wider memory system applications results in full-speed, error-free vices typically operate on only 750mW of power. operation without the need for additional discrete logic. The IDT70261 is packaged in a 100-pin TQFP. (1,2,3) Pin Configurations 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 A7L 76 50 A6R A8L 77 49 A7R A9L 78 48 A8R 47 A9R A10L 79 A11L 80 46 A10R 45 A11R A12L 81 A13L 82 44 A12R 43 LBL 83 A13R 42 UBL 84 LBR CEL 85 41 UBR 86 40 CER SEML 39 R/WL 87 SEMR 70261 VCC 88 38 GND (4) PNG100 89 OEL 37 R/WR I/O0L 90 36 OER 35 I/O1L 91 I/O15R 100-Pin TQFP GND Top View 92 34 GND I/O2L 93 33 I/O14R I/O3L 94 32 I/O13R I/O4L 95 31 I/O12R 96 I/O5L 30 I/O11R I/O6L 97 29 I/O10R I/O7L 98 28 I/O9R I/O8L 99 27 I/O8R I/O9L 100 26 I/O7R 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 3039 drw 02 Pin Names NOTES: 1. All VCC pins must be connected to power supply. Left Port Right Port Names 2. All GND pins must be connected to ground supply. CEL CER Chip Enable 3. Package body is approximately 14mm x 14mm x 1.4mm. 4. This package code is used to reference the package diagram. R/WL R/WR Read/Write Enable OEL OER Output Enable A0L - A13L A0R - A13R Address I/O0L - I/O15L I/O0R - I/O15R Data Input/Output Semaphore Enable SEML SEMR UBL UBR Upper Byte Select LBL LBR Lower Byte Select Interrupt Flag INTL INTR BUSYL BUSYR Busy Flag M/S Master or Slave Select VCC Power GND Ground 3039 tbl 01 6.422 N/C N/C N/C N/C N/C N/C A6L N/C A5L I/O10L I/O11L A4L I/O12L A3L A2L I/O13L A1L GND A0L I/O14L INTL I/O15L BUSYL VCC GND GND M/S I/O0R BUSYR I/O1R INTR I/O2R A0R VCC A1R I/O3R A2R I/O4R I/O5R A3R A4R I/O6R A5R N/C N/C N/C N/C N/C N/C N/C