HIGH-SPEED 3.3V 128/64K x 36 70V3599/89S SYNCHRONOUS DUAL-PORT STATIC RAM WITH 3.3V OR 2.5V INTERFACE Features: True Dual-Port memory cells which allow simultaneous Separate byte controls for multiplexed bus and bus access of the same memory location matching compatibility High-speed data access Dual Cycle Deselect (DCD) for Pipelined Output mode Commercial: 3.6ns (166MHz)/4.2ns (133MHz) (max.) LVTTL- compatible, 3.3V (150mV) power supply Industrial: 4.2ns (133MHz) (max.) for core Selectable Pipelined or Flow-Through output mode LVTTL compatible, selectable 3.3V (150mV) or 2.5V Counter enable and repeat features (100mV) power supply for I/Os and control signals on Dual chip enables allow for depth expansion without each port additional logic Industrial temperature range (-40C to +85C) is Full synchronous operation on both ports available at 133MHz. 6ns cycle time, 166MHz operation (12Gbps bandwidth) Available in a 208-pin Plastic Quad Flatpack (PQFP), Fast 3.6ns clock to data out 208-pin fine pitch Ball Grid Array (fpBGA), and 256-pin Ball 1.7ns setup to clock and 0.5ns hold on all control, data, and Grid Array (BGA) address inputs 166MHz Supports JTAG features compliant with IEEE 1149.1 Data input, address, byte enable and control registers Green parts available, see ordering information Self-timed write allows fast cycle time Functional Block Diagram BE3R BE3L BE2L BE2R BE1L BE1R BE0L BE0R FT/PIPEL 0a 1a 0b 1b 0c 1c 0d 1d 1d 0d 1c 0c 1b 0b 1a 0a FT/PIPER 1/0 1/0 ab c d dc b a R/WL R/WR CE0L CE0R 1 1 CE1R CE1L 0 0 B B B B B B B B 1/0 1/0 W W W W W W W W 0 1 2 3 3 2 1 0 L L L L R R R R OEL OER Dout0-8 L Dout0-8 R Dout9-17 L Dout9-17 R Dout18-26 L Dout18-26 R Dout27-35 L Dout27-35 R 1d 0d 1c 0c 1b 0b 1a 0a 0a 1a 0b 1b 0c 1c 0d 1d 0/1 0/1 FT/PIPEL FT/PIPER abcd dcba 128K x 36 MEMORY ARRAY I/O0L-I/O35L I/O0R - I/O35R Din L Din R , CLKR CLKL (1) (1) A A16L 16R Counter/ Counter/ A0L A0R ADDR R ADDR L Address REPEATL Address REPEATR ADSR ADSL Reg. Reg. CNTENL CNTENR 5617 tbl 01 TDI TCK NOTE: TMS JTAG TDO TRST 1. A16 is a NC for IDT70V3589. 1 Feb.03.20U11 REPEATR 70V3599/89S High-Speed 3.3V 128/64K x 36 Dual-Port Synchronous Static RAM Industrial and Commercial Temperature Ranges Description: The IDT70V3599/89 is a high-speed 128/64K x 36 bit synchronous or bidirectional data flow in bursts. An automatic power down feature, Dual-Port RAM. The memory array utilizes Dual-Port memory cells to controlled by CE0 and CE1, permits the on-chip circuitry of each port to allow simultaneous access of any address from both ports. Registers on enter a very low standby power mode. control, data, and address inputs provide minimal setup and hold The 70V3599/89 can support an operating voltage of either 3.3V or times. The timing latitude provided by this approach allows systems 2.5V on one or both ports, controllable by the OPT pins. The power supply to be designed with very short cycle times. With an input data register, the for the core of the device (VDD) remains at 3.3V. IDT70V3599/89 has been optimized for applications having unidirectional (1,2,3,4,5) Pin Configuration A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 (1 IO19L IO18L VSS A16L A12L A8L BE1L CLKL CNTENL A4L A0L VSS TDO NC VDD OPTL I/O17L ) B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 B13 B14 B15 B16 B17 I/O20R VSS I/O18R A13L A9L CE0L ADSL A5L A1L I/O15R TDI NC BE2L VSS VSS VDDQR I/O16L C1 C6 C2 C3 C4 C5 C7 C8 C9 C10 C11 C12 C13 C14 C15 C16 C17 VDDQL A14L I/O19R VDDQR PL/FTL NC A10L BE3L CE1L VSS R/WL A6L A2L VDD I/O16R I/O15L VSS D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 D16 D17 I/O22L VSS I/O21L A15L A11L A7L BE0L VDD OEL REPEATL A3L VDD I/O17R VDDQL I/O14L I/O14R I/O20L E1 E2 E3 E4 E14 E16 E17 E15 I/O23L I/O22R VDDQR I/O21R I/O12L I/O13R VSS I/O13L F1 F2 F3 F4 F14 F15 F16 F17 VDDQL I/O23R I/O24L VSS VSS I/O12R I/O11L VDDQR G1 G2 G3 G4 G14 G15 G16 G17 I/O26L VSS I/O25L I/O24R I/O9L VDDQL I/O10L I/O11R 70V3599/89 H3 H4 H1 H2 H14 H15 H16 H17 (6) BF208 VDD I/O26R VDDQR I/O25R VDD IO9R VSS I/O10R (6) BFG208 J1 J2 J3 J4 J14 J15 J16 J17 VDDQ VDD VSS VSS VSS VDD VSS VDDQR L 208-Pin fpBGA K2 K4 K15 K16 K1 K3 K14 K17 (7) I/O28R VSS I/O27R VSS I/O7R VDDQ I/O8R VSS Top View L L1 L2 L3 L4 L14 L15 L16 L17 VDDQR I/O27L I/O7L VSS I/O8L I/O29R I/O28L I/O6R M1 M2 M3 M4 M14 M15 M16 M17 VDDQL I/O29L I/O30R VSS I/O5R VDDQR VSS I/O6L N16 N17 N1 N2 N3 N4 N14 N15 I/O30L VDDQL I/O4R I/O5L I/O31L VSS I/O31R I/O3R P1 P2 P3 P4 P5 P6 P7 P8 P9 P10 P11 P12 P13 P14 P15 P16 P17 (1) I/O32R I/O32L VDDQR I/O35R TRST A12R A8R BE1R VDD CLKR CNTEN I/O2L I/O3L VSS I/O4L A16R A4R R R5 R6 R7 R8 R9 R10 R11 R16 R1 R2 R3 R4 R12 R13 R14 R15 R17 VSS I/O33L I/O34R TCK NC A13R A9R BE2R CE0R VSS ADSR A5R A1R VSS I/O1R VDDQR VDDQL T1 T2 T3 T4 T5 T8 T9 T15 T16 T17 T6 T7 T10 T11 T12 T13 T14 I/O34L VDDQL I/O33R TMS NC A14R A10R BE3R CE1R VSS R/WR A6R A2R VSS I/O0R VSS I/O2R U1 U2 U3 U4 U5 U6 U7 U8 U9 U10 U12 U13 U14 U16 U17 U15 VSS I/O35L PL/FTR NC A15R A11R A7R I/O1L BE0R VDD OER A3R A0R VDD OPTR I/O0L , 5617 drw 02c NOTES: 1. A16 is a NC for IDT70V3589. 2. All VDD pins must be connected to 3.3V power supply. 3. All VDDQ pins must be connected to appropriate power supply: 3.3V if OPT pin for that port is set to VIH (3.3V), and 2.5V if OPT pin for that port is set to VIL (0V). 4. All VSS pins must be connected to ground supply. 5. Package body is approximately 15mm x 15mm x 1.4mm with 0.8mm ball pitch. 6. This package code is used to reference the package diagram. 7. This text does not indicate orientation of the actual part-marking. 6.42 2 Feb.03.20