IDT70P5258ML
HIGH-SPEED
8K x 16 TriPort IDT70P525ML
IDT70V525ML
STATIC RAM
Features
High-speed access TriPort architecture allows simultaneous access to the
Industrial: 55ns (max.)
memory from all three ports
Low-power operation
Fully asynchronous operation from each of the three
IDT70P5258ML and IDT70P525ML ports: P1, P2, and P3
Active: 54mW (typ.)
IDT70P5258 supports 3.0V and 1.8V I/O's
Standby: 7.2W (typ.) Available in 144-ball 0.5mm-pitch fpBGA
IDT70V525ML Industrial temperature range (40C to +85C)
Active: 450mW (typ.)
Greeen parts available, see ordering information
Standby: 250W (typ.)
Functional Block Diagram
PORT 2
Address
A0P2-A11P2
Decode
BE0P1,BE1P1
CEP2
R/WP1
R/WP2
PORT 2
PORT 1
OEP2
OEP1
I/O
I/O
Control
Control
I/O0P2-I/O15P2
I/O0P1-I/O15P1
CEP3
Memory
R/WP3
PORT 3
Array
OEP3
I/O
Control
PORT 1
I/O0P3-I/O15P3
A0P1-A11P1
Address
BE0P1,BE1P1
Decode
PORT 3
Address A0P3-A11P3
Decode
Interrupt
BE0P1,BE1P1
OEP2,OEP3
Control
R/WP1
CEP2,CEP3
OEP1 R/WP2, R/WP3
INTP1 - P2 INTP3 - P1
INTP1 - P3
INTP2 - P1
,
5681 drw 01
JANUARY 2009
1
DSC 5681/5
2009 Integrated Device Technology, Inc.IDT70X525XML Preliminary
Low Power 4K x 8 TriPort Static RAM Industrial Temperature Range
Description
simultaneously accesses the same TriPort RAM location.
The IDT70X525X provides three independent ports with separate
The IDT70X525X is a high-speed 8K x 16 TriPort Static RAM designed
control, address, and I/O pins that permit independent, asynchronous
to be used in systems where multiple access into a common RAM is
required. This TriPort Static RAM offers increased system performance access for reads or writes to any location in memory. It is the users
responsibility to ensure data integrity when simultaneously accessing the
in multiprocessor systems that have a need to communicate in real time and
also offers added benefit for high-speed systems in which multiple access same memory location from mutiple ports. An automatic power down
is required in the same cycle. feature, controlled by BE0 and BE1 on Port 1 and CE on Port 2 and on
Port 3, permits the on-chip circuitry of each port to enter a very low power
The IDT70X525X is also designed to be used in systems where on-
chip hardware port arbitration is not needed. This part lends itself to those standby power mode.
The IDT70X525X is packaged in a 144-ball 0.5mm-pitch fpBGA.
systems which cannot tolerate wait states or are designed to be able to
externally arbitrated or withstand contention when more than one port
(1,2,3)
Pin Configurations
70(P/V)525XBZ
BZ-144
Top View
12/19/03
A1 A2 A3 A5 A6 A8 A9 A10 A11 A12
A4 A7
I/O7P3 I/O6P2 NC
I/O4P3 I/O3P2 I/O1P2 OEP3 R/WP2 A11P2 A9P2 A7P2 A6P2
B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12
(1)
I/O7P2 I/O6P3 VDD I/O2P3 A8P3 A5P3
I/O0P3 OEP2 CEP3 NC A10P3 A6P3
C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12
A11P3 A5P2
I/O9P2 Vss I/O5P2 I/O2P2 I/O0P2 R/WP3 CEP2 A10P2 A8P2 A4P3
D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12
(1)
I/O10P3 I/O8P2 I/O5P3 I/O3P3 I/O1P3
VDD VDD Vss A9P3 A7P3 A4P2 A3P2
E1 E2 E3 E4 E5 E6 E7 E8 E9 E10 E11 E12
I/O11P3 I/O11P2 I/O8P3 I/O4P2 Vss Vss A0P3 A3P3 A2P3
VDD Vss A2P2
F3
F1 F2 F4 F5 F6 F7 F8 F9 F10 F11 F12
(1) (1)
I/O9P3 Vss
I/O12P3 I/O12P2 VDD VDD Vss Vss Vss VDD A1P3 A0P2
G1 G2 G3 G4 G5 G6 G7 G8 G9 G10 G11 G12
(1)
I/O15P2 I/O13P3 I/O10P2 I/O13P2 Vss Vss Vss Vss Vss VDD A1P2 VDD
,
H6
H1 H2 H3 H4 H5 H7 H8 H9 H10 H11 H12
I/O14P3 I/O14P2 Vss Vss Vss Vss
I/O15P3 VDD VDD VDD INTP3P1INTP2P1
J1 J2 J3 J4 J5 J6 J7 J8 J9 J10 J11 J12
Vss Vss Vss
I/O2P1 I/O1P1 VDD Vss VDD VDD A0P1 INTP1P3 INTP1P2
K1
K2 K3 K4 K5 K6 K7 K8 K9 K10 K11 K12
Vss Vss A10P1 A3P1
I/O3P1 I/O0P1 I/O4P1 VDD VDD VDD A2P1 A1P1
L1 L2 L3 L4 L5 L6 L7 L8 L9 L10 L11 L12
A7P1 A4P1
I/O6P1 I/O5P1 I/O8P1 I/O14P1 A9P1
I/O10P1 I/O12P1 OEP1 BE0P1 NC
M1 M2 M3 M4 M5 M6 M7 M8 M9 M10 M11 M12
I/O7P1 I/O9P1 I/O11P1 I/O13P1 A8P1 A5P1
VDD I/O15P1 R/WP1 BE1P1 A11P1 A6P1
5681 drw 02
NOTES:
1. VDDQ for 70P5258.
6.422