CY7C1355C CY7C1357C 9-Mbit (256K x 36/512K x 18) Flow-Through SRAM with NoBL Architecture 1 Features Functional Description No Bus Latency (NoBL) architecture eliminates The CY7C1355C/CY7C1357C is a 3.3V, 256K x 36/512K x 18 dead cycles between write and read cycles Synchronous Flow-through Burst SRAM designed specifically to support unlimited true back-to-back Read/Write operations Can support up to 133-MHz bus operations with zero without the insertion of wait states. The wait states CY7C1355C/CY7C1357C is equipped with the advanced No Data is transferred on every clock Bus Latency (NoBL) logic required to enable consecutive Read/Write operations with data being transferred on every Pin compatible and functionally equivalent to ZBT clock cycle. This feature dramatically improves the throughput devices of data through the SRAM, especially in systems that require Internally self-timed output buffer control to eliminate frequent Write-Read transitions. the need to use OE All synchronous inputs pass through input registers controlled Registered inputs for flow-through operation by the rising edge of the clock. The clock input is qualified by Byte Write capability the Clock Enable (CEN) signal, which when deasserted suspends operation and extends the previous clock cycle. 3.3V/2.5V I/O power supply (V ) DDQ Maximum access delay from the clock rise is 6.5 ns (133-MHz Fast clock-to-output times device). 6.5 ns (for 133-MHz device) Write operations are controlled by the two or four Byte Write Select (BW ) and a Write Enable (WE) input. All writes are Clock Enable (CEN) pin to enable clock and suspend X conducted with on-chip synchronous self-timed write circuitry. operation Three synchronous Chip Enables (CE , CE , CE ) and an Synchronous self-timed writes 1 2 3 asynchronous Output Enable (OE) provide for easy bank Asynchronous Output Enable selection and output tri-state control. In order to avoid bus Available in JEDEC-standard and lead-free 100-Pin contention, the output drivers are synchronously tri-stated TQFP, lead-free and non lead-free 119-Ball BGA during the data portion of a write sequence. package and 165-Ball FBGA package Three chip enables for simple depth expansion. Automatic Power-down feature available using ZZ mode or CE deselect IEEE 1149.1 JTAG-Compatible Boundary Scan Burst Capabilitylinear or interleaved burst order Low standby power Selection Guide 133 MHz 100 MHz Unit Maximum Access Time 6.5 7.5 ns Maximum Operating Current 250 180 mA Maximum CMOS Standby Current 40 40 mA Note: 1. For best-practices recommendations, please refer to the Cypress application note System Design Guidelines on www.cypress.com. Cypress Semiconductor Corporation 198 Champion Court San Jose, CA 95134-1709 408-943-2600 Document : 38-05539 Rev. *E Revised September 14, 2006 + Feedback CY7C1355C CY7C1357C 1 Logic Block Diagram CY7C1355C (256K x 36) ADDRESS A0, A1, A A1 REGISTER A1 D1 Q1 A0 A0 D0 Q0 MODE BURST CE ADV/LD CLK C LOGIC C CEN WRITE ADDRESS REGISTER O U T P D S U A E T T N ADV/LD A S B MEMORY BWA WRITE E U WRITE REGISTRY S ARRAY DQs DRIVERS F BWB AND DATA COHERENCY T DQPA A F E CONTROL LOGIC DQPB BWC M E E DQPC P R R BWD DQPD S S I WE E N G INPUT E REGISTER OE READ LOGIC CE1 CE2 CE3 SLEEP ZZ CONTROL 2 Logic Block Diagram CY7C1357C (512K x 18) ADDRESS A0, A1, A A1 A1 REGISTER D1 Q1 A0 A0 D0 Q0 MODE BURST CE ADV/LD LOGIC CLK C C CEN WRITE ADDRESS REGISTER O U T P D S U A E T T ADV/LD N A S B MEMORY BWA WRITE E U WRITE REGISTRY S ARRAY DQs DRIVERS F T BWB AND DATA COHERENCY DQPA A F E CONTROL LOGIC DQPB M E E P R R S S I WE N E G INPUT E REGISTER OE READ LOGIC CE1 CE2 CE3 SLEEP ZZ CONTROL Document : 38-05539 Rev. *E Page 2 of 28 + Feedback