128K x 36 71V35761S/SA 3.3V Synchronous SRAMs 3.3V I/O, Pipelined Outputs Burst Counter, Single Cycle Deselect Features 128K x 36 memory configurations Power down controlled by ZZ input Supports high system speed: 3.3V I/O Commercial: Optional - Boundary Scan JTAG Interface (IEEE 1149.1 200MHz 3.1ns clock access time compliant) Commercial and Industrial: Packaged in a JEDEC Standard 100-pin plastic thin quad 183MHz 3.3ns clock access time flatpack (TQFP), 119 ball grid array (BGA) and 165 fine 166MHz 3.5ns clock access time pitch ball grid array LBO input selects interleaved or linear burst mode Industrial temperature range (40C to +85C) is available for 3.3V core power supply selected speeds Self-timed write cycle with global write control (GW), byte write Green parts available, see ordering information enable (BWE), and byte writes (BWx) Functional Block Diagram LBO ADV INTERNAL Burst ADDRESS CEN Sequence 128K x 36- CLK 2 Burst 17/18 Binary BIT Logic Counter ADSC A0* MEMORY Q0 CLR ARRAY A1* Q1 ADSP 2 CLK EN A0,A1 A2A17 A0 - A16/17 ADDRESS 36 REGISTER 36 17/18 GW Byte 1 BWE Write Register Byte 1 Write Driver BW1 9 Byte 2 Byte 2 Write Register Write Driver BW2 9 Byte 3 Write Register Byte 3 Write Driver BW3 9 Byte 4 Byte 4 Write Register Write Driver BW4 9 OUTPUT REGISTER CE Q D CS0 Enable DATA CS1 Register INPUT CLK EN REGISTER ZZ Powerdown DQ Enable Delay Register OE OUTPUT BUFFER OE , 36 I/O0 I/O31 I/OP1 I/OP4 5301 drw 01 TMS TDI JTAG TDO TCK (SA Version) TRST (Optional) 1 May.18.2071V35761, 128K x 36, 3.3V Synchronous SRAMs with11 3.3V I/O, Pipelined Outputs, Burst Counter, Single Cycle Deselect Commercial and Industrial Temperature Ranges for one cycle before it is available on the next rising clock edge. If Description burst mode operation is selected (ADV=LOW), the subsequent The IDT71V35761 are high-speed SRAMs organized as three cycles of output data will be available to the user on the next 128K x 36. The IDT71V35761 SRAMs contain write, data, address and three rising clock edges. The order of these three addresses are control registers. Internal logic allows the SRAM to generate a self-timed defined by the internal burst counter and the LBO input pin. write based upon a decision which can be left until the end of the write cycle. The IDT71V35761 SRAM utilizes a high-performance CMOS process The burst mode feature offers the highest level of performance to the and is packaged in a JEDEC standard 14mm x 20mm 100-pin thin plastic system designer, as the IDT71V35761 can provide four cycles of data for quad flatpack (TQFP) as well as a 119 ball grid array (BGA) and 165 fine a single address presented to the SRAM. An internal burst address pitch ball grid array(fBGA). counter accepts the first cycle address from the processor, initiating the access sequence. The first cycle of output data will be pipelined Pin Description Summary A0-A17 Address Inputs Input Synchronous Chip Enable Input Synchronous CE CS0, CS1 Chip Selects Input Synchronous Output Enable Input Asynchronous OE GW Global Write Enable Input Synchronous Byte Write Enable Input Synchronous BWE (1) Individual Byte Write Selects Input Synchronous BW1, BW2, BW3, BW4 CLK Clock Input N/A Burst Address Advance Input Synchronous ADV ADSC Address Status (Cache Controller) Input Synchronous Address Status (Processor) Input Synchronous ADSP LBO Linear / Interleaved Burst Order Input DC TMS Test Mode Select Input Synchronous TDI Test Data Input Input Synchronous TCK Test Clock Input N/A TDO Test Data Output Output Synchronous JTAG Reset (Optional) Input Asynchronous TRST ZZ Sleep Mode Input Asynchronous I/O0-I/O31, I/OP1-I/OP4 Data Input / Output I/O Synchronous VDD, VDDQ Core Power, I/O Power Supply N/A VSS Ground Supply N/A 5301 tbl 01 6.422 May.18.20