70V7519S HIGH-SPEED 3.3V 256K x 36 SYNCHRONOUS BANK-SWITCHABLE DUAL-PORT STATIC RAM WITH 3.3V OR 2.5V INTERFACE 1.5ns setup to clock and 0.5ns hold on all control, data, and Features: address inputs 200MHz 256K x 36 Synchronous Bank-Switchable Dual-ported Data input, address, byte enable and control registers SRAM Architecture Self-timed write allows fast cycle time 64 independent 4K x 36 banks Separate byte controls for multiplexed bus and bus 9 megabits of memory on chip matching compatibility Bank access controlled via bank address pins LVTTL- compatible, 3.3V (150mV) power supply High-speed data access for core Commercial: 3.4ns(200MHz)/3.6ns (166MHz)/4.2ns LVTTL compatible, selectable 3.3V (150mV) or 2.5V (100mV) (133MHz) (max.) power supply for I/Os and control signals on each port Industrial: 3.6ns (166MHz)/4.2ns (133MHz) (max.) Industrial temperature range (-40C to +85C) is Selectable Pipelined or Flow-Through output mode available at 166MHz and 133MHz Counter enable and repeat features Available in a 208-pin fine pitch Ball Grid Array (fpBGA) Dual chip enables allow for depth expansion without and 256-pin Ball Grid Array (BGA) additional logic Supports JTAG features compliant with IEEE 1149.1 Full synchronous operation on both ports Green parts available, see ordering information 5ns cycle time, 200MHz operation (14Gbps bandwidth) Fast 3.4ns clock to data out Functional Block Diagram PL/FTL PL/FTR OPTL OPTR CLKL CLKR ADSL ADSR CNTENL CNTENR REPEATL REPEATR R/WL R/WR MUX CE0L CE0R CONTROL CONTROL CE1L LOGIC CE1R LOGIC BE3L 4Kx36 BE3R BE2L MEMORY BE2R BE1L ARRAY BE1R (BANK 0) BE0L BE0R OEL OER MUX MUX I/O I/O I/O0L-35L I/O0R-35R CONTROL CONTROL 4Kx36 MEMORY ARRAY (BANK 1) A11R A11L ADDRESS ADDRESS DECODE DECODE A0R A0L MUX BA5R BA5L BA4R BA4L BA3R BA3L BANK BANK DECODE BA2R BA2L DECODE BA1L MUX BA1R BA0R BA0L 4Kx36 MEMORY ARRAY (BANK 63) NOTE: MUX 1. The Bank-Switchable dual-port uses a true SRAM , core instead of the traditional dual-port SRAM core. 5618 drw 01 TMS As a result, it has unique operating characteristics. TDI TCK JTAG Please refer to the functional description on page 19 TDO TRST for details. NOVEMBER 2019 1 DSC 5618/11 2019 Integrated Device Technology, Inc.U11 REPEATR 70V7519S High-Speed 256K x 36 Synchronous Bank-Switchable Dual-Port Static RAM Industrial and Commercial Temperature Ranges Description: The IDT70V7519 is a high-speed 256Kx36 (9Mbit) synchronous register, the IDT70V7519 has been optimized for applications having Bank-Switchable Dual-Ported SRAM organized into 64 independent unidirectional or bidirectional data flow in bursts. An automatic power down 4Kx36 banks. The device has two independent ports with separate feature, controlled by CE0 and CE1, permits the on-chip circuitry of each control, address, and I/O pins for each port, allowing each port to access port to enter a very low standby power mode. The dual chip enables also any 4Kx36 memory block not already accessed by the other port. facilitate depth expansion. Accesses by the ports into specific banks are controlled via the bank The 70V7519 can support an operating voltage of either 3.3V or 2.5V address pins under the user s direct control. on one or both ports, controllable by the OPT pins. The power supply for Registers on control, data, and address inputs provide minimal setup the core of the device(VDD) remains at 3.3V. Please refer also to the and hold times. The timing latitude provided by this approach allows functional description on page 19. systems to be designed with very short cycle times. With an input data (1,2,3,4) Pin Configuration A1 A2 A3 A6 A7 A8 A9 A11 A12 A13 A14 A17 A4 A5 A10 A15 A16 IO19L IO18L VSS BA4L BA0L A8L BE1L CLKL CNTENL A4L A0L VSS TDO NC VDD OPTL I/O17L B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 B13 B14 B15 B16 B17 I/O20R VSS I/O18R TDI BA5L BA1L A9L BE2L CE0L VSS ADSL A5L A1L VSS VDDQR I/O16L I/O15R C1 C6 C2 C3 C4 C5 C7 C8 C9 C10 C11 C12 C13 C14 C15 C16 C17 VDDQL BA2L I/O19R VDDQR PL/FTL NC A10L BE3L CE1L VSS R/WL A6L A2L VDD I/O16R I/O15L VSS D1 D2 D6 D9 D11 D3 D4 D5 D7 D8 D10 D12 D13 D14 D15 D16 D17 I/O22L VSS A11L VDD REPEATL I/O21L I/O20L BA3L A7L BE0L OEL A3L VDD I/O17R VDDQL I/O14L I/O14R E1 E2 E3 E4 E14 E15 E16 E17 I/O23L I/O22R VDDQR I/O21R I/O12L I/O13R VSS I/O13L F1 F2 F3 F14 F15 F16 F17 F4 VDDQL I/O23R I/O24L VSS VSS I/O12R I/O11L VDDQR G1 G2 G3 G4 G14 G15 G16 G17 I/O26L VSS I/O25L I/O24R I/O9L VDDQL I/O10L I/O11R H1 H2 H3 H4 H16 H17 H14 H15 70V7519 VDD I/O26R VDDQR I/O25R VDD IO9R VSS I/O10R (5) BF208 J1 J2 J3 J4 J14 J15 J16 J17 VDDQL VDD VSS VSS VSS VDD VSS VDDQR 208-Pin fpBGA K1 K2 K3 K4 K14 K15 K16 K17 (6) I/O28R VSS I/O27R VSS Top View I/O7R VDDQL I/O8R VSS L1 L2 L3 L4 L14 L15 L16 L17 I/O29R I/O28L VDDQR I/O27L I/O6R I/O7L VSS I/O8L M1 M2 M3 M4 M16 M17 M14 M15 VDDQL I/O29L I/O30R VSS VSS I/O6L I/O5R VDDQR N16 N17 N1 N2 N3 N4 N14 N15 I/O4R I/O5L I/O31L VSS I/O31R I/O30L I/O3R VDDQL P1 P2 P3 P4 P5 P7 P8 P9 P10 P11 P12 P14 P15 P16 P17 P6 P13 I/O32R I/O32L VDDQR I/O35R TRST BA0R A8R BE1R VDD CLKR CNTENR I/O2L I/O3L VSS I/O4L BA4R A4R R5 R6 R7 R8 R9 R10 R11 R16 R1 R2 R3 R4 R12 R13 R14 R15 R17 BA5R BA1R A9R BE2R CE0R VSS ADSR I/O1R VSS I/O33L I/O34R TCK A5R A1R VSS VDDQL VDDQR T2 T3 T1 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 I/O34L VDDQL I/O33R TMS NC BA2R A10R BE3R CE1R VSS R/WR A6R A2R VSS I/O0R VSS I/O2R U1 U2 U3 U4 U5 U6 U7 U8 U9 U10 U12 U13 U14 U16 U17 U15 VSS I/O35L PL/FTR NC BA3R A11R A7R BE0R VDD OER A3R A0R VDD OPTR I/O0L I/O1L 5618 drw 02c NOTES: 1. All VDD pins must be connected to 3.3V power supply. 2. All VDDQ pins must be connected to appropriate power supply: 3.3V if OPT pin for that port is set to VIH (3.3V), and 2.5V if OPT pin for that port is set to VIL (0V). 3. All VSS pins must be connected to ground supply. 4. Package body is approximately 15mm x 15mm x 1.4mm with 0.8mm ball pitch. 5. This package code is used to reference the package diagram. 6. This text does not indicate orientation of the actual part-marking. 6.42 2