CY62256EV18LL-70SNXI Infineon

Please note that Cypress is an Infineon Technologies Company. The document following this cover page is marked as Cypress document as this is the company that originally developed the product. Please note that Infineon will continue to offer the product to new and existing customers as part of the Infineon product portfolio. Continuity of document content The fact that Infineon offers the following product as part of the Infineon product portfolio does not lead to any changes to this document. Future revisions will occur when appropriate, and any changes will be set out on the document history page. Continuity of ordering part numbers Infineon continues to support existing part numbers. Please continue to use the ordering part numbers listed in the datasheet for ordering. www.infineon.com CY62256EV18 MoBL 256-Kbit (32 K 8) Static RAM 256-Kbit (32 K 8) Static RAM Features Functional Description Very high speed: 70 ns The CY62256EV18 is a high performance CMOS static RAM module organized as 32 K words by 8-bits. This device features Temperature ranges: advanced circuit design to provide ultra low active current. This Industrial: 40 C to +85 C is ideal for providing More Battery Life (MoBL ) in portable applications such as cellular telephones. The device also has an Wide voltage range: 1.65 V to 2.25 V automatic power-down feature that significantly reduces power Pin compatible with CY62256N consumption when addresses are not toggling. Placing the device in standby mode reduces power consumption by more Ultra low standby power than 99 percent when deselected (CE HIGH). The eight input Typical standby current: 1 A and output pins (I/O through I/O ) are placed in a high 0 7 Maximum standby current: 4 A impedance state when the device is deselected (CE HIGH), the outputs are disabled (OE HIGH), or a write operation is in Ultra low active power progress (CE LOW and WE LOW). Typical active current: 1.3 mA at f = 1 MHz To write to the device, take chip enable (CE) LOW and write Easy memory expansion with CE and OE features enable (WE) LOW. Data on the eight I/O pins is then written into the location specified on the address pin (A through A ). Automatic power-down when deselected 0 14 To read from the device, take chip enable (CE LOW) and output Complementary metal oxide semiconductor (CMOS) for enable (OE) LOW while forcing write enable (WE) HIGH. Under optimum speed and power these conditions, the contents of the memory location specified Offered in Pb-free 28-pin Narrow SOIC package by the address pins appear on the I/O pins. For a complete list of related documentation, click here. Logic Block Diagram I/O 0 INPUTBUFFER I/O 1 A 10 A 9 I/O 2 A 8 A 7 A I/O 3 6 32K x 8 A 5 ARRAY A I/O 4 4 A 3 A 2 I/O 5 CE I/O 6 POWER WE COLUMN DOWN DECODER I/O 7 OE Cypress Semiconductor Corporation 198 Champion Court San Jose, CA 95134-1709 408-943-2600 Document Number: 001-69650 Rev. *D Revised September 21, 2015 ROW DECODER A 14 A 13 A 12 A 11 A 1 A 0 SENSE AMPS