CMOS SuperSync FIFO 16,384 x 9 IDT72261LA IDT72271LA 32,768 x 9 LEAD FINISH (SnPb) ARE IN EOL PROCESS - LAST TIME BUY EXPIRES JUNE 15, 2018 Available in the 64-pin Thin Quad Flat Pack (TQFP) and the 64- FEATURES: pin Slim Thin Quad Flat Pack (STQFP) Choose among the following memory organizations: High-performance submicron CMOS technology IDT72261LA 16,384 x 9 Industrial temperature range (40C to +85C) is available IDT72271LA 32,768 x 9 Green parts available, see ordering information Pin-compatible with the IDT72281/72291 SuperSync FIFOs 10ns read/write cycle time (8ns access time) DESCRIPTION: Fixed, low first word data latency time Auto power down minimizes standby power consumption The IDT72261LA/72271LA are exceptionally deep, high speed, CMOS Master Reset clears entire FIFO First-In-First-Out (FIFO) memories with clocked read and write controls. Partial Reset clears data, but retains programmable settings These FIFOs offer numerous improvements over previous SuperSync Retransmit operation with fixed, low first word data latency time FIFOs, including the following: Empty, Full and Half-Full flags signal FIFO status The limitation of the frequency of one clock input with respect to the other Programmable Almost-Empty and Almost-Full flags, each flag has been removed. The Frequency Select pin (FS) has been removed, can default to one of two preselected offsets thus it is no longer necessary to select which of the two clock inputs, Program partial flags by either serial or parallel means RCLK or WCLK, is running at the higher frequency. Select IDT Standard timing (using EF and FF flags) or First The period required by the retransmit operation is now fixed and short. Word Fall Through timing (using OR and IR flags) The first word data latency period, from the time the first word is written Output enable puts data outputs into high impedance state to an empty FIFO to the time it can be read, is now fixed and short. (The Easily expandable in depth and width variable clock cycle counting delay associated with the latency period found Independent Read and Write clocks (permit reading and writing on previous SuperSync devices has been eliminated on this SuperSync simultaneously) family.) FUNCTIONAL BLOCK DIAGRAM D0 -D8 WEN WCLK LD SEN OFFSET REGISTER INPUT REGISTER FF/IR PAF FLAG EF/OR WRITE CONTROL LOGIC PAE LOGIC HF FWFT/SI RAM ARRAY 16,384 x 9 32,768 x 9 WRITE POINTER READ POINTER READ CONTROL RT LOGIC OUTPUT REGISTER MRS RESET RCLK LOGIC PRS REN Q0 -Q8 4671 drw 01 OE IDT and the IDT logo are registered trademarks of Integrated Device Technology, Inc. The SuperSync FIFO is a trademark of Integrated Device Technology, Inc. FEBRUARY 2018 COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES 1 2018 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. DSC-4671/6IDT72261LA/72271LA SuperSync FIFO COMMERCIAL AND INDUSTRIAL 16,384 x 9 and 32,768 x 9 TEMPERATURE RANGES The frequencies of both the RCLK and the WCLK signals may vary from 0 DESCRIPTION (CONTINUED) to fMAX with complete independence. There are no restrictions on the SuperSync FIFOs are particularly appropriate for network, video, telecom- frequency of one clock input with respect to the other. munications, data communications and other applications that need to buffer There are two possible timing modes of operation with these devices: large amounts of data. IDT Standard mode and First Word Fall Through (FWFT) mode. The input port is controlled by a Write Clock (WCLK) input and a Write Enable In IDT Standard mode, the first word written to an empty FIFO will not (WEN) input. Data is written into the FIFO on every rising edge of WCLK when appear on the data output lines unless a specific read operation is WEN is asserted. The output port is controlled by a Read Clock (RCLK) input performed. A read operation, which consists of activating REN and enabling and Read Enable (REN) input. Data is read from the FIFO on every rising a rising RCLK edge, will shift the word from internal memory to the data output edge of RCLK when REN is asserted. An Output Enable (OE) input is provided lines. for three-state control of the outputs. PIN CONFIGURATIONS PIN 1 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 (3) WEN DNC 1 48 (3) SEN DNC 2 47 (1) DC GND 3 46 (3) VCC DNC 4 45 (3) VCC DNC 5 44 (2) GND VCC 6 43 (3) (2) DNC GND 7 42 (3) (2) DNC GND 8 41 (3) (2) DNC GND 9 40 (2) GND GND 10 39 (3) (2) 11 38 DNC GND (3) (2) DNC GND 12 37 (2) 13 36 Q8 GND (2) 35 Q7 GND 14 15 34 Q6 D8 16 33 GND D7 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 4671 drw 02 TQFP (PN64-1, ORDER CODE: PF) STQFP (PP64-1, ORDER CODE: TF) TOP VIEW NOTES: 1. DC = Dont Care. Must be tied to GND or VCC, cannot be left open. 2. This pin may either be tied to ground or left open. 3. DNC = Do Not Connect. 2 WCLK PRS D5 MRS D4 D3 LD D2 FWFT/SI D1 GND D0 FF/IR PAF GND HF Q0 Q1 VCC PAE GND EF/OR Q2 RCLK Q3 REN VCC RT Q4 OE Q5 D6