3.3 VOLT CMOS SuperSync FIFO 32,768 x 18 IDT72V275 65,536 x 18 IDT72V285 LEAD FINISH (SnPb) ARE IN EOL PROCESS - LAST TIME BUY EXPIRES JUNE 15, 2018 Slim Thin Quad Flat Pack (STQFP) FEATURES: High-performance submicron CMOS technology Choose among the following memory organizations: Industrial temperature range (-40C to +85C) is available IDT72V275 32,768 x 18 Green parts are available, see ordering information IDT72V285 65,536 x 18 Pin-compatible with the IDT72V255/72V265 SuperSync FIFOs 10ns read/write cycle time (6.5ns access time) DESCRIPTION: Fixed, low first word data latency time The IDT72V275/72V285 are exceptionally deep, high speed, CMOS Auto power down minimizes standby power consumption First-In-First-Out (FIFO) memories with clocked read and write controls. Master Reset clears entire FIFO These FIFOs offer numerous improvements over previous SuperSync Partial Reset clears data, but retains programmable FIFOs, including the following: settings The limitation of the frequency of one clock input with respect to the other Retransmit operation with fixed, low first word data has been removed. The Frequency Select pin (FS) has been removed, latency time thus it is no longer necessary to select which of the two clock inputs, RCLK Empty, Full and Half-Full flags signal FIFO status or WCLK, is running at the higher frequency. Programmable Almost-Empty and Almost-Full flags, each flag can The period required by the retransmit operation is now fixed and short. default to one of two preselected offsets The first word data latency period, from the time the first word is written to Program partial flags by either serial or parallel means an empty FIFO to the time it can be read, is now fixed and short. (The Select IDT Standard timing (using EFEFEF and FFFFFF flags) or First Word EFEF FFFF Fall Through timing (using OROROR and IRIRIR flags) variable clock cycle counting delay associated with the latency period OROR IRIR Output enable puts data outputs into high impedance state found on previous SuperSync devices has been eliminated on this Easily expandable in depth and width SuperSync family.) Independent Read and Write clocks (permit reading and writing SuperSync FIFOs are particularly appropriate for network, video, telecom- simultaneously) munications, data communications and other applications that need to buffer Available in the 64-pin Thin Quad Flat Pack (TQFP) and the 64-pin large amounts of data. FUNCTIONAL BLOCK DIAGRAM D0 -D17 WEN WCLK LD SEN INPUT REGISTER OFFSET REGISTER FF/IR PAF FLAG EF/OR WRITE CONTROL LOGIC PAE LOGIC HF FWFT/SI RAM ARRAY 32,768 x 18 65,536 x 18 WRITE POINTER READ POINTER READ RT CONTROL LOGIC OUTPUT REGISTER MRS RESET RCLK LOGIC PRS REN 4512 drw 01 Q0 -Q17 OE IDT and the IDT logo are registered trademarks of Integrated Device Technology, Inc. The SuperSync FIFO is a trademark of Integrated Device Technology, Inc. COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES FEBRUARY 2018 1 DSC-4512/5TM IDT72V275/72V285 3.3V CMOS SUPERSYNC FIFO COMMERCIAL AND INDUSTRIAL 32,768 x 18 and 65,536 x 18 TEMPERATURE RANGES In IDT Standard mode, the first word written to an empty FIFO will not appear DESCRIPTION (Continued) on the data output lines unless a specific read operation is performed. A read The input port is controlled by a Write Clock (WCLK) input and a Write Enable operation, which consists of activating REN and enabling a rising RCLK edge, (WEN) input. Data is written into the FIFO on every rising edge of WCLK when will shift the word from internal memory to the data output lines. WEN is asserted. The output port is controlled by a Read Clock (RCLK) input In FWFT mode, the first word written to an empty FIFO is clocked directly and Read Enable (REN) input. Data is read from the FIFO on every rising to the data output lines after three transitions of the RCLK signal. A REN does edge of RCLK when REN is asserted. An Output Enable (OE) input is provided not have to be asserted for accessing the first word. However, subsequent for three-state control of the outputs. words written to the FIFO do require a LOW on REN for access. The state of The frequencies of both the RCLK and the WCLK signals may vary from 0 the FWFT/SI input during Master Reset determines the timing mode in use. to fMAX with complete independence. There are no restrictions on the frequency For applications requiring more data storage capacity than a single FIFO of the one clock input with respect to the other. can provide, the FWFT timing mode permits depth expansion by chaining FIFOs There are two possible timing modes of operation with these devices: IDT in series (i.e. the data outputs of one FIFO are connected to the corresponding Standard mode and First Word Fall Through (FWFT) mode. data inputs of the next). No external logic is required. PIN CONFIGURATIONS PIN 1 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 WEN 1 48 Q17 SEN 2 47 Q16 (1) GND DC 3 46 Q15 VCC 4 45 5 44 Q14 GND VCC 6 43 D17 Q13 7 42 D16 Q12 8 41 D15 Q11 9 40 D14 GND 10 39 D13 Q10 11 38 D12 Q9 12 37 D11 Q8 D10 13 36 Q7 14 35 D9 Q6 D8 15 34 GND D7 16 33 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 4512 drw 02 TQFP (PN64, order code: PF) STQFP (PP64, order code: TF) TOP VIEW NOTE: 1. DC = Dont Care. Must be tied to GND or VCC, cannot be left open. 2 WCLK PRS D5 MRS D4 D3 LD D2 FWFT/SI GND D1 D0 FF/IR GND PAF Q0 HF VCC Q1 PAE GND EF/OR Q2 RCLK Q3 REN VCC RT Q4 Q5 OE D6