QUAD PCM CODEC WITH IDT821034 PROGRAMMABLE GAIN DESCRIPTION: FEATURES: 4 channel CODEC with on-chip digital filters The IDT821034 is a single-chip, four channel PCM CODEC with on- Software Selectable A-law/m-law companding chip filters and programmable gain setting. This device provides both Programmable gain setting -Law and A-Law companding digital-to-analog and analog-to-digital Automatic master clock frequency selection: 2.048MHz, 4.096 conversions based on ITU-T G.711 - G.714 specifications. The digital MHz or 8.192MHz filters in IDT821034 provides the necessary transmit and receive filtering Flexible PCM interface with up to 128 programmable time slots, for voice telephone circuit to interface with time-division multiplexed data rate from 512 kbits/s to 8.192 Mbits/s systems. The IDT821034 has a flexible PCM interface with software 5 SLIC signaling pins per channel selectable timing modes and independently programmable time slot for Flexible Serial Control Interface to microcontroller each transmit and receive channel. It also integrates the SLIC signaling Software programmable timing modes functions through internal registers. The CODEC and SLIC control/status TTL and CMOS compatible digital I/O registers are accessed via the Serial Control Interface. Meets or exceeds ITU-T G.711 - G.714 requirements The IDT821034 can be used in digital telecommunication applications +5 V single power supply such as PBX, Central Office Switch, Digital Telephone and Integrated Voice/ Low power consumption: 100mW Typ. Data Access Unit. Operating temperature range: -40 C to +85 C Packages available: 52 pin PQFP FUNCTIONAL BLOCK DIAGRAM GSX0 DX VFXI0 - DR A/D PCM FS ++ Interface BCLK Channel 0 +2.5V TSX D/A VFRO0 DSP CO O 0(4 - 2) SLIC Interface I/O CI Serial I/O 0(1 - 0) CS Control CCLK Interface Channel 1 Channel 2 Timing MCLK Channel 3 The IDT logo is a registered trademark of Integrated Device Technology, Inc INDUSTRIAL TEMPERATURE RANGE MAY 13, 2003 1 2003 Integrated Device Technology, Inc. DSC-6032/3 IDT821034 QUAD PCM CODEC WITH PROGRAMMABLE GAIN INDUSTRIAL TEMPERATURE RANGE PIN CONFIGURATIONS GNDA 40 26 I/O0 0 GNDA 41 25 GND VFXI1 42 24 CS GSX1 CI 43 23 VFRO1 44 22 CO VDDA 45 21 CCLK GNDA 46 20 BCLK 52-Pin PQFP VDDA 47 19 MCLK VFRO2 48 18 FS GSX2 49 17 TSX VFXI2 50 16 DR GNDA 51 15 VDD 52 14 GNDA DX PIN DESCRIPTION Name Type Pin Number Description GNDA -- 46 Analog Ground. 51 All ground pins should be connected to the ground plane of the circuit board. 52 40 41 VDDA -- 47 +5 V Analog Power Supply. 45 This pin should be bypassed to ground using 0.1 F capacitor. All power supply pins should be connected to the power plane of the circuit board. VFRO3 O 3 Voice Frequency Receiver Output. VFRO2 48 This is the output of receive power amplifier. It can drive 2000 (or greater) load. VFRO1 44 VFRO0 37 GSX3 O 2 Gain Setting Transmit Amplifier Output. GSX2 49 This pin is the output of the gain setting amplifier, and the input to the differential transmit filter. It should be GSX1 43 connected to the corresponding VFXI pin through a resistive network to set the transmit gain. Refer to Figure GSX0 38 5 for details. VFXI3 I 1 Voice Frequency Transmitter Input. VFXI2 50 This pin is the input to the gain setting amplifier in the transmit path. VFXI1 42 VFXI0 39 O3 4 O 9 SLIC Signaling Output for Channel 3. O3 3 10 O3 2 11 O2 4 4 SLIC Signaling Output for Channel 2. O2 3 O 5 O2 2 6 2 VFXI3 1 39 VFXI0 GSX3 2 38 GSX0 VFRO3 3 37 VFRO0 O2 4 4 CNF 36 O2 3 5 35 O1 4 O2 2 6 34 O1 3 I/O2 1 7 33 O1 2 I/O2 0 8 32 I/O1 1 O3 4 9 31 I/O1 0 O3 3 10 O0 4 30 O3 2 11 29 O0 3 I/O3 1 12 O0 2 28 I/O3 0 13 27 I/O0 1