Synchronization Management Unit for IEEE 82P33831 1588 and 10G/40G Synchronous Ethernet SHORT FORM DATA SHEET Any reference input (IN3 to IN14) can be designated as external sync HIGHLIGHTS pulse inputs (1 PPS, 2 kHz, 4 kHz or 8 kHz) associated with a select- Synchronization Management Unit (SMU) provides tools to manage able reference clock input physical layer and packet based synchronous clocks for IEEE 1588 / FRSYNC 8K 1PPS and MFRSYNC 2K 1PPS output sync pulses PTP Telecom Profile applications that are aligned with the selected external input sync pulse input and Supports independent IEEE 1588 and Synchronous Ethernet frequency locked to the associated reference clock input (SyncE) timing paths DPLL1 and DPLL2 can be configured with bandwidths between 0.09 Combo mode provides SyncE physical layer frequency support for mHz and 567 Hz IEEE 1588 Telecom Boundary Clocks (T-BC) and Telecom Time DPLL1 and DPLL2 lock to input references with frequencies between Slave Clocks (T-TSC) per G.8273.2 1 PPS and 650 MHz Digital PLL 1 (DPLL1) and DPLL 2 can be configured as Digitally DPLL3 locks to input references with frequencies between 8 kHz and Controlled Oscillators (DCOs) for PTP clock synthesis 650 MHz DCO frequency resolution is (77760 / 1638400) * 2 -48 or DPLL1 and DPLL2 comply with ITU-T G.8262 for Synchronous ~1.686305041e-10 ppm Ethernet Equipment Clock (EEC), and G.813 for Synchronous Equip- DPLL1 and DPLL2 generate G.8262 compliant SyncE clocks ment Clock (SEC) and Telcordia GR-253-CORE for Stratum 3 and Two independent Time of Day (ToD) counters/time accumulators, one SONET Minimum Clock (SMC) associated with each of DPLL1 and DPLL2, can be used to track dif- DPLL1 and DPLL2 generate clocks with PDH, TDM, GSM, CPRI/ ferences between the two time domains and to time-stamp external OBSAI, 10/100/1000 Ethernet and GNSS frequencies these clocks events are directly available on OUT1 DPLL3 performs rate conversions to frequency synchronization inter- DPLL1 and DPLL2 can be configured as DCOs to synthesize IEEE faces or for other general purpose timing applications 1588 clocks APLL3 is Voltage Controlled Crystal Oscillator (VCXO) based and DPLL3 generates N x 8 kHz clocks up to 100 MHz that are output on generates clocks with jitter <0.3 ps RMS (10 kHz to 20 MHz) for: OUT9 and OUT10 10GBASE-R, 10GBASE-W and 40GBASE-R APLL1, APLL2 and APLL3 can be connected to DPLL1 or DPLL2 APLL1 and APLL2 generate clocks with jitter < 1 ps RMS (12 kHz to APLL1 and APLL2 generate 10/100/1000 Ethernet, 10G Ethernet, or 20 MHz) for: 1000BASE-T and 1000BASE-X SONET/SDH frequencies Fractional-N input dividers support a wide range of reference fre- APLL3 generates 10G Ethernet, WAN-PHY and LAN-PHY frequen- quencies cies Locks to 1 Pulse Per Second (PPS) references Any of eight common TCXO/OCXO frequencies can be used for the DPLLs, APLL1 and APLL2 can be configured from an external System Clock: 10 MHz, 12.8 MHz, 13 MHz, 19.44 MHz, 20 MHz, EEPROM after reset 24.576 MHz, 25 MHz or 30.72 MHz FEATURES The I2C slave interface can be used by a host processor to access Composite clock inputs (IN1 and IN2) accept 64 kHz synchronization the control and status registers interface signals per ITU-T G.703 The I2C master interface can automatically load a device configura- Differential reference inputs (IN3 to IN8) accept clock frequencies tion from an external EEPROM after reset APLL3 must be config- between 1 PPS and 650 MHz ured via the I2C slave interface Single ended inputs (IN9 to IN14) accept reference clock frequencies DPLL1 or DPLL3 can be connected to an internal composite clock between 1 PPS and 162.5 MHz generator that outputs its 64 kHz synchronization signal on OUT8 Loss of Signal (LOS) pins (LOS0 to LOS3) can be assigned to any Differential outputs OUT3 to OUT6 output clocks with frequencies clock reference input between 1 PPS and 650 MHz Reference monitors qualify/disqualify references depending on activ- Differential outputs OUT11 and OUT12 output clocks with frequen- ity, frequency and LOS pins cies up to 650 MHz Automatic reference selection state machines select the active refer- Single ended outputs OUT1, OUT2 and OUT7 output clocks with fre- ence for each DPLL based on the reference monitors, priority tables, quencies between 1 PPS and 125 MHz revertive and non-revertive settings and other programmable settings Single ended outputs OUT9 and OUT10 output clocks N*8kHz multi- Fractional-N input dividers enable the DPLLs to lock to a wide range ples up to 100 MHz of reference clock frequencies including: 10/100/1000 Ethernet, 10G DPLL1 and DPLL2 support independent programmable delays for Ethernet, OTN, SONET/SDH, PDH, TDM, GSM, CPRI and GNSS each of IN3 to IN14 the delay for each input is programmable in frequencies steps of 0.61 ns with a range of ~78 ns 82P33831 REVISION 2 12/08/14 1 2014 Integrated Device Technology, Inc.82P33831 SHORT FORM DATA SHEET The input to output phase delay of DPLL1 and DPLL2 is program- PON OLT mable in steps of 0.0745 ps with a total range of 20 s LTE eNodeB The clock phase of each of the output dividers for OUT1 (from IEEE 1588 / PTP Telecom Profile clock synthesizer APLL1) to OUT7 is individually programmable in steps of ~200 ps ITU-T G.8273.2 Telecom Boundary Clock (T-BC) and Telecom with a total range of +/-180 Time Slave Clock (T-TSC) 1149.1 JTAG Boundary Scan ITU-T G.8264 Synchronous Equipment Timing Source (SETS) 144-pin CABGA green package ITU-T G.8263 Packet-based Equipment Clock (PEC) ITU-T G.8262 Synchronous Ethernet Equipment Clock (EEC) APPLICATIONS ITU-T G.813 Synchronous Equipment Clock (SEC) Access routers, edge routers, core routers Telcordia GR-253-CORE Stratum 3 Clock (S3) and SONET Mini- Carrier Ethernet switches mum Clock (SMC) Multiservice access platforms DESCRIPTION The 82P33831 Synchronization Management Unit (SMU) provides tools to manage timing references, clock sources and timing paths for IEEE 1588 / Precision Time Protocol (PTP) and Synchronous Ethernet (SyncE) based clocks. The device supports up to three independent timing paths that control: PTP clock synthesis SyncE clock generation and general purpose frequency translation. The device supports physical layer timing with Digital PLLs (DPLLs) and it supports packet based timing with Digitally Controlled Oscillators (DCOs). Input-to- input, input-to-output and output-to- output phase skew can all be precisely managed. The device outputs low-jitter clocks that can directly synchronize 40GBASE-R, 10GBASE-R and 10GBASE-W and lower-rate Ethernet interfaces as well as CPRI/OBSAI, SONET/SDH and PDH interfaces and IEEE 1588 Time Stamp Units (TSUs). The 82P33831 accepts six differential reference inputs and six single ended reference inputs that can operate at common GNSS, Ethernet, SONET/SDH and PDH frequencies that range in frequency from 1 Pulse Per Second (PPS) to 650 MHz. The device also provides two Alternate Mark Inversion (AMI) inputs for Composite Clock (CC) signals bearing 64 kHz, 8 kHz and 0.4 kHz synchronization information. The references are continu- ally monitored for loss of signal and for frequency offset per user programmed thresholds. All of the references are available to all three DPLLs. The active reference for each DPLL is determined by forced selection or by automatic selection based on user programmed priorities and locking allow- ances and based on the reference monitors and LOS inputs. The 82P33831 can accept a clock reference and an associated phase locked sync signal as a pair. DPLL1 or DPLL2 can lock to the clock refer- ence and align the frame sync and multi-frame sync outputs with the paired sync input. The device allows any of the differential or single ended refer- ence inputs to be configured as sync inputs that can be associated with any of the other differential or single ended reference inputs. The input sync signals can have a frequency of 1 PPS, 2 kHz, 4 kHz or 8 kHz. This feature enables DPLL1 or DPLL2 to phase align its frame sync and multi-frame sync outputs with a sync input without the need use a low bandwidth setting to lock directly to the sync input. DPLL1 and DPLL2 support four primary operating modes: Free-Run, Locked, Holdover and DCO. In Free-Run mode the DPLLs synthesize clocks based on the system clock alone. In Locked mode the DPLLs filter reference clock jitter with the selected bandwidth. In Locked mode, the long-term output frequency accuracy is the same as the long term frequency accuracy of the selected input reference. In Holdover mode, the DPLL uses fre- quency data acquired while in Locked mode to generate accurate frequencies when input references are not available. In DCO mode the DPLL con- trol loop is opened and the DCO can be controlled by a PTP clock recovery servo running on an external processor to synthesize PTP clocks. The 82P33831 requires a system clock for its reference monitors and other digital circuitry. The frequency accuracy of the system clock deter- mines the frequency accuracy of the DPLLs in Free-Run mode. The frequency stability of the system clock determines the frequency stability of the DPLLs in Free-Run mode and in Holdover mode and it affects the wander generation of the DPLLs in Locked and DCO modes. When used with a suitable system clock, DPLL1 and DPLL2 meet the frequency accuracy, pull-in, hold-in, pull-out, noise generation, noise toler- ance, transient response, and holdover performance requirements of the following applications: ITU-T G.8262/G.813 EEC/SEC options 1 and 2, ITU- T G.8263, ITU-T G.8273.2, Telcordia GR-1244 Stratum 3 (S3), Telcordia GR-253-CORE Stratum 3 (S3) and SONET Minimum Clock (SMC). DPLL1 and DPLL2 can be configured with a range of selectable filtering bandwidths from 0.09 mHz to 567 Hz. The 17 mHz bandwidth can be used to lock the DPLL directly to a 1 PPS reference. The 69 mHz and the 92 mHz bandwidths can be used for G.8273.2. The 92 mHz bandwidth can be used for G.8262/G.813 Option 2 or Telcordia GR-253-CORE S3 or SMC applications. The bandwidths in the range 1.1 Hz to 8.9 Hz can be used for G.8262/G.813 Option 1 applications. Bandwidths above 10 Hz can be used in jitter attenuation and rate conversion applications. DPLL1 and DPLL2 are each connected to Time of Day (ToD) counters or time accumulators these ToD counters/time accumulators can be used to track differences between the two time domains and to time-stamp external events by using reference inputs as triggers. DPLL3 supports three primary operation modes: Free-Run, Locked and Holdover. DPLL3 is a wideband (BW > 25Hz) frequency translator that can be used, for example, to convert a recovered line clock to a 1.544 MHz or 2.048 MHz synchronization interface clock. SYNCHRONIZATION MANAGEMENT UNIT FOR IEEE 1588 AND 2 REVISION 2 12/08/14 10G/40G SYNCHRONOUS ETHERNET