Low Skew, 1-to-2 83026I-01 Data Sheet Differential-to-LVCMOS/LVTTL Fanout Buffer GENERAL DESCRIPTION FEATURES The 83026I-01 is a low skew, 1-to-2 Differential-to-LVC- Two LVCMOS / LVTTL outputs MOS/LVTTL Fanout Buffer. The differential input can Differential CLK, nCLK input pair accept most differential signal types (LVPECL, LVDS, LVHSTL, HCSL and SSTL) and translate to two sin- CLK, nCLK pair can accept the following differential gle-ended LVCMOS/LVTTL outputs. The small 8-lead SOIC input levels: LVPECL, LVDS, LVHSTL, HCSL, SSTL footprint makes this device ideal for use in applications with Maximum output frequency: 350MHz limited board space. Output skew: 15ps (maximum) Part-to-part skew: 600ps (maximum) Additive phase jitter, RMS: 0.03ps (typical) Small 8 lead SOIC package saves board space 3.3V core, 3.3V, 2.5V or 1.8V output operating supply -40C to 85C ambient operating temperature Available in lead-free RoHS (6) package BLOCK DIAGRAM PIN ASSIGNMENT VDD 1 8 VDDO CLK 2 7 Q0 nCLK 3 6 Q1 Q0 OE 4 5 GND CLK nCLK Q1 83026I-01 8-Lead SOIC 3.8mm x 4.8mm, x 1.47mm package body OE M Package Top View VDD 1 8 VDDO CLK 2 7 Q0 nCLK 3 6 Q1 4 5 OE GND 83026I-01 8-Lead TSSOP 4.40mm x 3.0mm x 0.925mm package body G Package Top View 2015 Integrated Device Technology, Inc 1 December 15, 201583026I-01 Data Sheet TABLE 1. PIN DESCRIPTIONS Number Name Type Description 1 V Power Positive supply pin. DD CLK 2 Input Pulldown Non-inverting differential clock input. Pullup/ 3 nCLK Input Inverting differential clock input. V /2 default when left oating. DD Pulldown Output enable. When HIGH, outputs are enabled. When LOW, outputs are in 4 OE Input Pullup High Impedance State. LVCMOS / LVTTL interface levels. 5 GND Power Power supply ground. 6 Q1 Output Clock output. LVCMOS / LVTTL interface levels. Q0 7 Output Clock output. LVCMOS / LVTTL interface levels. 8 V Power Output supply pin. DDO NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values. TABLE 2. PIN CHARACTERISTICS Symbol Parameter Test Conditions Minimum Typical Maximum Units C Input Capacitance 4 pF IN V , V = 3.465V 17 pF DD DDO Power Dissipation Capacitance C V = 3.465V, V = 2.625V 16 pF PD DD DDO (per output) V = 3.465V, V = 1.95V 15 pF DD DDO R Input Pullup Resistor 51 k PULLUP R Input Pulldown Resistor 51 k PULLDOWN V , V = 3.3V 7 DD DDO R Output Impedance V = 3.3V, V = 2.5V 8 OUT DD DDO V = 3.3V, V = 1.8V 10 DD DDO TABLE 3. CONTROL FUNCTION TABLE Input Outputs OE Q0, Q1 0 HiZ 1 Active 2015 Integrated Device Technology, Inc 2 December 15, 2015