1-to-1 2.5V, 3.3V 830S21I-01 Differential-to-LVCMOS/LVTTL Translator Datasheet General Description Features 830S21I-01 is a 1-to-1 Differential-to- LVCMOS/ LVTTL translator One LVCMOS/LVTTL output and a member of the family of High Performance Clock Solutions Differential CLK, nCLK input pair from IDT. The differential input is highly flexible and can accept the CLK, nCLK pair can accept the following differential following input types: LVPECL, LVDS, LVHSTL, SSTL and HCSL. input levels: LVPECL, LVDS, LVHSTL, SSTL, HCSL The small 8-lead SOIC footprint makes this device ideal for use in Maximum output frequency: 350MHz applications with limited board space. Part-to-part skew: 525ps (maximum) Additive phase jitter, RMS: 0.11ps (typical) Small 8 lead SOIC package saves board space Full 3.3V and 2.5V operating supply -40C to 85C ambient operating temperature Available in lead-free (RoHS 6) package Block Diagram Pin Assignment Pullup/Pulldown nc 1 8 VDD CLK CLK Q 2 7 Q nCLK nc Pullup/Pulldown 3 6 nCLK OE 4 5 GND Pullup OE 830S21I-01 8-Lead SOIC 3.9mm x 4.9mm x 1.375mm package body M Package Top View 2015 Integrated Device Technology, Inc 1 December 10, 2015830S21I-01 Datasheet Table 1. Pin Descriptions Number Name Type Description 1, 6 nc Unused No connect. Pullup/ 2 CLK Input Non-inverting differential clock input. Pulldown Pullup/ 3 nCLK Input Inverting differential clock input. Pulldown 4 OE Input Pullup Output enable pin. See Table 3. LVCMOS / LVTTL interface levels. 5 GND Power Power supply ground. 7 Q Output Single-ended clock output. LVCMOS / LVTTL interface levels. 8V Power Positive supply pin. DD NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values. Table 2. Pin Characteristics Symbol Parameter Test Conditions Minimum Typical Maximum Units C Input Capacitance 4 pF IN R Input Pullup Resistor 51 k PULLUP R Input Pulldown Resistor 51 k PULLDOWN V = 3.465V 10 pF DD C Power Dissipation Capacitance PD V = 2.625V 8 pF DD V = 3.3V 10 DD R Output Impedance OUT V = 2.5V 12 DD Function Tables Table 3. OE Configuration Table Input OE Operation 0 Output Q is in a high-impedance state. 1 (default) Output Q is enabled. 2015 Integrated Device Technology, Inc 2 December 10, 2015