1-to-2, LVCMOS/LVTTL-to-Differential 85222-02 HSTL Translator DATASHEET GENERAL DESCRIPTION FEATURES The 85222-02 is a 1-to-2 LVCMOS / LVTTL-to-Differential HSTL Two differential HSTL outputs translator. The 85222-02 has one single ended clock input. The One LVCMOS/LVTTL clock input single-ended clock input accepts LVCMOS or LVTTL input levels and translates them to HSTL levels. The small outline 8-pin SOIC CLK input can accept the following input levels: package makes this device ideal for applications where space, high LVCMOS or LVTTL performance and low power are important. Maximum output frequency: 350MHz Part-to-part skew: 250ps (maximum) Propagation delay: 1.25ns (maximum) V : 1.4V (maximum) OH Output crossover voltage: 0.68V - 0.9V Full 3.3V operating supply voltage 0C to 70C ambient operating temperature Industrial temperature information available upon request Available in lead-free RoHS compliant package BLOCK DIAGRAM PIN ASSIGNMENT Q0 Q0 1 8 VDD nQ0 2 7 CLK nQ0 Pulldown CLK Q1 3 6 nc Q1 4 5 nQ1 GND nQ1 85222-02 8-Lead SOIC 3.90mm x 4.92mm x 1.37mm body package M Package Top View 85222-02 REVISION B 6/15/15 1 2015 Integrated Device Technology, Inc.85222-02 DATA SHEET TABLE 1. PIN DESCRIPTIONS Number Name Type Description 1, 2 Q0, nQ0 Output Differential output pair. HSTL interface levels. 3, 4 Q1, nQ1 Output Differential output pair. HSTL interface levels. 5 GND Power Power supply ground. 6 nc Unused No connect. 7 CLK Input Pulldown LVCMOS / LVTTL clock input. 8V Power Positive supply pin. DD NOTE: Pulldown refers to internal input resistors. See Table 2, Pin Characteristics, for typical values. NOTE: Unused output pairs must be terminated. TABLE 2. PIN CHARACTERISTICS Symbol Parameter Test Conditions Minimum Typical Maximum Units C Input Capacitance 4 pF IN R Input Pulldown Resistor 51 k PULLDOWN 1-TO-2, LVCMOS/LVTTL-TODIFFERENTIAL 2 REVISION B 6/15/15 HSTL TRANSLATOR