VDDO Low Skew, 1-to-4, Differential-to-HSTL 8523 Fanout Buffer DATA SHEET General Description Features The 8523 is a low skew, high performance 1-to-4 Four differential output HSTL compatible outputs Differential-to-HSTL Fanout Buffer.The 8523 has two selectable Selectable differential CLK, nCLK or LVPECL clock inputs clock inputs.The CLK, nCLK pair can accept most standard CLK, nCLK pair can accept the following differential input levels: differential input levels.The PCLK, nPCLK pair can accept LVPECL, LVPECL, LVDS, HSTL, HCSL, SSTL CML, or SSTL input levels.The clock enable is internally PCLK, nPCLK pair can accept the following differential input synchronized to eliminate runt pulses on the outputs during levels: LVPECL, CML, SSTL asynchronous assertion/deassertion of the clock enable pin. Maximum output frequency: 650MHz Guaranteed output and part-to-part skew characteristics make the Translates any single-ended input signal to HSTL levels with 8523 ideal for those applications demanding well defined resistor bias on nCLK input performance and repeatability. Additive phase jitter, RMS: 0.082ps (typical), 100MHz f OUT Additive phase jitter, RMS: 0.190ps (typical), 120MHz f OUT Output skew: 30ps (maximum) Part-to-part skew: 200ps (maximum) 3.3V core, 1.8V output operating supply 0C to 70C ambient operating temperature Available in lead-free (RoHS 6) package Block Diagram Pin Assignment Pullup GND 1 20 Q0 CLK EN D CLK EN 2 19 nQ0 Q CLK SEL 3 18 VDDO LE CLKPulldown CLK 4 17 Q1 Pullup 0 nCLK Q0 nCLK 5 16 nQ1 nQ0 PCLK 6 15 Q2 Pulldown PCLK nPCLK Pullup 1 7 14 nQ2 nPCLK Q1 nc 8 13 nQ1 nc Pulldown 9 12 Q3 CLK SEL nQ3 VDD 10 11 Q2 nQ2 8523 Q3 20-LeadTSSOP nQ3 6.5mm x 4.4mm x 0.925mm package body G Package TopView 8523 Rev E 6/15/15 1 2015 Integrated Device Technology, Inc.8523 DATA SHEET Table 1. Pin Descriptions Number Name Type Description 1 GND Power Power supply ground. Synchronizing clock enable. When HIGH, clock outputs follow clock input. 2 CLK EN Input Pullup When LOW, Qx outputs are forced low, nQx outputs are forced high. LVCMOS / LVTTL interface levels. Clock select input. When HIGH, selects differential PCLK, nPCLK inputs. When 3 CLK SEL Input Pulldown LOW, selects CLK, nCLK inputs. LVCMOS / LVTTL interface levels. 4 CLK Input Pulldown Non-inverting differential clock input. 5 nCLK Input Pullup Inverting differential clock input. 6 PCLK Input Pulldown Non-inverting differential LVPECL clock input. 7 nPCLK Input Pullup Inverting differential LVPECL clock input. 8, 9 nc Unused No connect. Power Positive supply pin. 10 V DD 11, 12 nQ3, Q3 Output Differential output pair. HSTL interface levels. Power Output supply pins. 13, 18 V DDO 14, 15 nQ2, Q2 Output Differential output pair. HSTL interface levels. 16, 17 nQ1, Q1 Output Differential output pair. HSTL interface levels. 19, 20 nQ0, Q0 Output Differential output pair. HSTL interface levels. NOTE: Pullup and Pulldown refer to internal input resistors. SeeTable 2, Pin Characteristics, for typical values. Table 2. Pin Characteristics Symbol Parameter Test Conditions Minimum Typical Maximum Units Input Capacitance 4pF C IN Input Pullup Resistor 51 k R PULLUP R Input Pulldown Resistor 51 k PULLDOWN LOW SKEW, 1-TO-4, DIFFERENTIAL-TO-HSTL FANOUT BUFFER 2 Rev E 6/15/15