CLK0 Low Skew, 1-to-5, Differential-To- ICS85304I-01 3.3V LVPECL Fanout Buffer DATASHEET General Description Features The ICS85304I-01 is a low skew, high performance 1-to-5 Five 3.3V differential LVPECL output pairs Differential-to-3.3V LVPECL fanout buffer. The ICS85304I-01 has Selectable differential CLKx, nCLKx input pairs two selectable clock inputs. The CLKx, nCLKx pairs can accept most CLKx, nCLKx input pairs can accept the following differential standard differential input levels. The clock enable is internally levels: LVDS, LVPECL, LVHSTL and HCSL levels synchronized to eliminate runt clock pulses on the outputs during Maximum output frequency: 650MHz asynchronous assertion/ deassertion of the clock enable pin. Translates any single-ended input signal to 3.3V LVPECL levels Guaranteed output and part-to-part skew characteristics make the with resistor bias on nCLKx inputs ICS85304I-01 ideal for those applications demanding well defined Output skew: 60ps (maximum) performance and repeatability. Part-to-part skew: 300ps (maximum) Propagation delay: 2.1ns (maximum) Full 3.3V supply mode -40C to 85C ambient operating temperature Lead-free (RoHS 6) package Block Diagram Pin Assignment Pullup CLK EN D Q0 1 20 VCC nQ0 2 19 CLK EN Q Q1 3 18 VCC LE Pulldown CLK0 nQ1 4 17 nCLK1 Pullup 00 Q0 nCLK0 Q2 5 16 CLK1 nQ2 6 15 VEE nQ0 Pulldown CLK1 1 Q3 7 14 nCLK0 Pullup 1 nCLK1 nQ3 8 13 Q1 Q4 9 12 CLK SEL nQ1 Pulldown CLK SEL nQ4 10 11 VCC Q2 nQ2 ICS85304I-01 Q3 20-Lead TSSOP nQ3 6.5mm x 4.4mm x 0.925mm package body Q4 G Package nQ4 Top View ICS85304AGI-01 REVISION A FEBRUARY 4, 2013 1 2013 Integrated Device Technology, Inc.ICS85304I-01 Data Sheet LOW SKEW, 1-TO-5 DIFFERENTIAL-TO- 3.3V LVPECL FANOUT BUFFER Pin Description and Pin Characteristics Tables Table 1. Pin Descriptions Number Name Type Description 1, 2 Output Differential output pair. LVPECL interface levels. Q0, nQ0 3, 4 Output Differential output pair. LVPECL interface levels. Q1, nQ1 5, 6 Q2, nQ2 Output Differential output pair. LVPECL interface levels. 7, 8 Output Differential output pair. LVPECL interface levels. Q3, nQ3 9, 10 Output Differential output pair. LVPECL interface levels. Q4, nQ4 Power Positive supply pins. 11, 18, 20 V CC Clock select input. When HIGH, selects CLK1, nCLK1 inputs. When LOW, 12 CLK SEL Input Pulldown selects CLK0, nCLK0 inputs. LVTTL/LVCMOS interface levels. 13 CLK0 Input Pulldown Non-inverting differential clock input. 14 nCLK0 Input Pullup Inverting differential clock input. 15 V Power Negative supply pin. EE 16 CLK1 Input Pulldown Non-inverting differential clock input. 17 nCLK1 Input Pullup Inverting differential clock input. Synchronizing clock enable. When HIGH, clock outputs follow clock input. 19 CLK EN Input Pullup When LOW, Qx outputs are forced LOW, nQx outputs are forced HIGH. LVTTL/LVCMOS interface levels. NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values. Table 2. Pin Characteristics Symbol Parameter Test Conditions Minimum Typical Maximum Units Input Capacitance 4 pF C IN R Input Pulldown Resistor 51 k PULLDOWN R Input Pullup Resistor 51 k PULLUP ICS85304AGI-01 REVISION A FEBRUARY 4, 2013 2 2013 Integrated Device Technology, Inc.