Low Skew, 1-to-16 Differential-to-3.3V 8530I-01 LVPECL Fanout Buffer Datasheet General Description Features The 8530I-01is a low skew, 1-to-16 Differential- to-3.3V LVPECL Sixteen differential 3.3V LVPECL output pairs Fanout Buffer. The CLK, nCLK pair can accept most standard CLK, nCLK input pair differential input levels. The high gain differential amplifier accepts CLK, nCLK pair can accept the following differential input peak-to-peak input voltages as small as 150mV as long as the levels: LVPECL, LVDS, LVHSTL, HCSL, SSTL common mode voltage is within the specified minimum and Maximum output frequency: 500MHz maximum range. Translates any single-ended input signal to 3.3V LVPECL levels Guaranteed output and part-to-part skew characteristics make the with a resistor bias on nCLK input 8530I-01 ideal for those clock distribution applications demanding Output skew: 75ps (maximum) well defined performance and repeatability. Additive phase jitter, RMS 106.25MHz: 0.162ps (typical) Full 3.3V supply voltage -40C to 85C ambient operating temperature Available in lead-free (RoHS 6) package Block Diagram Pin Assignment Pulldown CLK0 Pullup nCLK0 48 47 46 45 44 43 42 41 40 39 38 37 Q15 Q0 VCCO 1 CLK 36 Q11 2 VCCO 35 nQ15 nQ0 nQ11 3 nQ0 34 Q1 Q14 Q10 4 33 Q0 nQ10 5 32 nQ1 nQ1 nQ14 VEE Q1 6 31 Q2 Q13 Q9 7 VEE 30 nQ13 nQ9 nQ2 nQ2 8 29 Q8 9 Q2 28 Q12 Q3 nQ8 10 nQ3 27 nQ3 nQ12 VCCO 11 Q3 26 VCC 12 VCCO 25 Q11 Q4 13 14 15 16 17 18 19 20 21 22 23 24 nQ11 nQ4 Q5 Q10 8530I-01 nQ5 nQ10 48-Lead TQFP, E-Pad Q9 Q6 7mm x 7mm x 1.0mm package body nQ9 nQ6 Y Package Q8 Q7 Top View nQ8 nQ7 2015 Integrated Device Technology, Inc. 1 Revision B, December 1, 2015 VCC VCCO VCCO nQ12 Q7 Q12 nQ7 nQ13 Q6 Q13 nQ6 VEE VEE nQ14 Q5 Q14 nQ5 nQ15 Q4 Q15 VCCO nQ4 VCCO nCLK8530I-01 Datasheet Pin Description and Pin Characteristic Tables Table 1. Pin Descriptions Number Name Type Description 1, 11, 14, 24, 25, 35, 38, 48 V Power Output power supply pins. CCO 2, 3 Q11, nQ11 Output Differential output pair. LVPECL interface levels. 4, 5 Q10, nQ10 Output Differential output pair. LVPECL interface levels. 6, 19, 30, 43 V Power Negative power supply pins. EE 7, 8 Q9, nQ9 Output Differential output pair. LVPECL interface levels. 9, 10 Q8, nQ8 Output Differential output pair. LVPECL interface levels. 12, 13 V Power Positive power supply pins. CC 15, 16 Q7, nQ7 Output Differential output pair. LVPECL interface levels. 17, 18 Q6, nQ6 Output Differential output pair. LVPECL interface levels. 20, 21 Q5, nQ5 Output Differential output pair. LVPECL interface levels. 22, 23 Q4, nQ4 Output Differential output pair. LVPECL interface levels. 26, 27 Q3, nQ3 Output Differential output pair. LVPECL interface levels. 28, 29 Q2, nQ2 Output Differential output pair. LVPECL interface levels. 31, 32 Q1, nQ1 Output Differential output pair. LVPECL interface levels. 33, 34 Q0, nQ0 Output Differential output pair. LVPECL interface levels. 36 CLK Input Pulldown Non-inverting differential clock input. 37 nCLK Input Pullup Inverting differential clock input. 39, 40 Q15, nQ15 Output Differential output pair. LVPECL interface levels. 41. 42 Q14, nQ14 Output Differential output pair. LVPECL interface levels. 44, 45 Q13, nQ13 Output Differential output pair. LVPECL interface levels. 46, 47 Q12, nQ12 Output Differential output pair. LVPECL interface levels. NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values. Table 2. Pin Characteristics Symbol Parameter Test Conditions Minimum Typical Maximum Units C Input Capacitance 4 pF IN R Input Pullup Resistor 51 k PULLUP R Input Pulldown Resistor 51 k PULLDOWN 2015 Integrated Device Technology, Inc. 2 Revision B, December 1, 2015