FSEL 0 1 FSEL Programmable FemtoClock NG 3.3V, 83PN15639 2.5V LVPECL Oscillator Replacement Datasheet General Description Features The 83PN15639 is a programmable LVPECL synthesizer that is for- Fourth Generation FemtoClock NG technology ward footprint compatible with standard 5mm x 7mm oscillators. Footprint compatible with 5mm x 7mm differential oscillators The device uses IDTs fourth generation FemtoClock NG technolo- One differential LVPECL output pair gy for an optimum of high clock frequency and low phase noise per- formance. Forward footprint compatibility means that a board Crystal oscillator interface which can also be overdriven using a designed to accommodate the crystal oscillator interface and the op- single-ended reference clock tional control pins are also fully compatible with a canned oscillator Output frequency: 100MHz - 156.25390625MHz footprint - the canned oscillator will drop onto the 10-VFQFN foot- Crystal/input frequency: 25MHz, 12pF parallel resonant crystal print for second sourcing purposes. This capability provides design- ers with programability and lead time advantages of silicon/crystal VCO range: 2GHz 2.5GHz based solutions while maintaining compatibility with industry stan- RMS phase jitter 156.25MHz, 10kHz 1MHz: 0.179ps (typical) dard 5mm x 7mm oscillator footprints for ease of supply chain man- th Full 3.3V or 2.5V operating supply agement. Oscillator-level performance is maintained with IDTs 4 NG PLL technology, which delivers sub Generation FemtoClock -40C to 85C ambient operating temperature 0.2ps RMS phase jitter. Lead-free (RoHS 6) packaging The 83PN15639 defaults to 156.25MHz using a 25MHz crystal but can also be set to one of four different frequency multiplier settings to support a wide variety of applications. The table below shows some of the more common application settings. Common Applications and Settings FSEL1, FSEL0 XTAL (MHz) Output Frequency (MHz) Application(s) 00 25 100 PCI Express 01 25 125 Ethernet 10 25 150 SAS, Embedded Processor Pin Assignment 11 (default) 25 156.25 10 Gigabit Ethernet (default) 10 GbE, Frequency 11 (default) 25.000625 156.25390625 Margining (+25ppm) 10 9 OE 1 8 V CC nQ 2 7 Block Diagram RESERVED Pullup V 3 6 Q EE OE 45 XTAL IN PFD FemtoClock NG Q 25MHz & OSC VCO nQ N LPF 2 - 2.5GHz XTAL OUT 83PN15639 M 10-Lead VFQFN 5mm x 7mm x 1mm Pullup FSEL0 Control package body Pullup Logic NR Package FSEL1 Top View 2016 Integrated Device Technology, Inc 1 Revision B August 16, 2016 XTAL OUT XTAL IN83PN15639 Datasheet Pin Descriptions and Characteristics Table 1. Pin Descriptions Number Name Type Description 1 OE Input Pullup Output enable. LVCMOS/LVTTL interface levels. 2 RESERVED Reserve Reserved pin. Do not connect. 3V Power Negative supply pin. EE 4, XTAL OUT Input Crystal oscillator interface XTAL IN is the input, XTAL OUT is the output. 5 XTAL IN 6, 7 Q, nQ Output Differential output pair. LVPECL interface levels. 8V Power Power supply pin. CC Output divider control inputs. Sets the output divider value to one of four 9 FSEL0 Input Pullup values. LVCMOS/LVTTL interface levels. Output divider control inputs. Sets the output divider value to one of four 10 FSEL1 Input Pullup values. LVCMOS/LVTTL interface levels. NOTE: Pullup refers to internal input resistors. See Table 2, Pin Characteristics, for typical values. Table 2. Pin Characteristics Symbol Parameter Test Conditions Minimum Typical Maximum Units C Input Capacitance OE, FSEL0, FSEL1 3.5 pF IN R Input Pullup Resistor 51 k PULLUP 2016 Integrated Device Technology, Inc. 2 Revision B August 16, 2016