FSEL 0 1 FSEL Programmable FemtoClock NG 83PN187I LVPECL Oscillator Replacement Data Sheet General Description Features The 83PN187I is a programmable LVPECL synthesizer that is Fourth Generation FemtoClock Next Generation (NG) technology forward footprint compatible with standard 5mm x 7mm oscillators. The device uses IDTs fourth generation FemtoClock NG Footprint compatible with 5mm x 7mm differential oscillators technology for an optimum of high clock frequency and low phase One differential LVPECL output pair noise performance. Forward footprint compatibility means that a Crystal oscillator interface can also be overdriven by a board designed to accommodate the crystal oscillator interface and single-ended reference clock the optional control pins is also fully compatible with a canned Output frequency range: 125MHz 187.5MHz oscillator footprint - the canned oscillator will drop onto the 10-VFQFN footprint for second sourcing purposes. This capability Crystal/input frequency: 25MHz, 12pF parallel resonant crystal provides designers with programability and lead time advantages of VCO range: 2GHz 2.5GHz silicon/crystal based solutions while maintaining compatibility with Cycle-to-cycle jitter: 10ps (maximum), 3.3V5% industry standard 5mm x 7mm oscillator footprints for ease of supply RMS phase jitter 156.25MHz, 12kHz 20MHz: chain management. Oscillator-level performance is maintained with 0.339ps (typical) th IDTs 4 Generation FemtoClock NG PLL technology, which Full 3.3V or 2.5V operating supply delivers sub 0.5ps rms phase jitter. -40C to 85C ambient operating temperature The 83PN187I defaults to 150MHz using a 25MHz crystal with 2 programming pins floating (pulled down/pulled up with internal pullup Available in lead-free (RoHS 6) package or pulldown resistors) but can also be set to 4 different frequency multiplier settings to support a wide variety of applications. The below table shows some of the more common application settings. Common Applications and Settings FSEL 1:0 XTAL (MHz) Output Frequency (MHz) Application(s) 00 25 156.25 XAUI, 10GigE Pin Assignment 01 25 187.5 8Gig Fibre Channel 10 25 125 Ethernet SAS, Embedded 10 9 11 (default) 25 150 Processor OE 1 8 V CC nQ 7 RESERVED 2 Block Diagram V 3 6 Q EE 45 Pullup OE XTAL IN PFD FemtoClock NG Q OSC & VCO N nQ XTAL OUT 83PN187I 10-Lead VFQFN M 5mm x 7mm x 1mm package body K Package Pullup FSEL0 Top View Control Pullup FSEL1 Logic 2016 Integrated Device Technology, Inc 1 Revision A March 4, 2016 XTAL OUT XTAL IN83PN187I Data Sheet Table 1. Pin Descriptions Number Name Type Description 1 OE Input Pullup Output enable. LVCMOS/LVTTL interface levels. 2 RESERVED Reserve Reserved pin. Do not connect. 3V Power Negative supply pin. EE 4, XTAL OUT Crystal oscillator interface XTAL IN is the input, XTAL OUT is the output. This Input 5 XTAL IN oscillator interface can also be driven by a single-ended reference clock. 6, 7 Q, nQ Output Differential output pair. LVPECL interface levels. 8V Power Power supply pin. CC Output divider control inputs. Sets the output divider value to one of four values. 9 FSEL0 Input Pullup See Table 3. LVCMOS/LVTTL interface levels. Output divider control inputs. Sets the output divider value to one of four values. 10 FSEL1 Input Pullup See Table 3. LVCMOS/LVTTL interface levels NOTE: Pullup refers to internal input resistors. See Table 2, Pin Characteristics, for typical values. Table 2. Pin Characteristics Symbol Parameter Test Conditions Minimum Typical Maximum Units C Input Capacitance 4pF IN R Input Pullup Resistor 51 k PULLUP Function Table Table 3. Divider Function Table FSEL 1:0 M Value N Value 0 0 100 16 0 1 90 12 1 0 80 16 1 1 (default) 84 14 2016 Integrated Device Technology, Inc 2 Revision A March 4, 2016