N1 N0 Programmable FemtoClock LVPECL 83PR226I-01 Oscillator Replacement Datasheet Description Features The 83PR226I-01 is a programmable LVPECL synthesizer that is Footprint compatible with 5mm x 7mm differential oscillators forward footprint compatible with standard 5mm x 7mm oscillators. One differential LVPECL output pair Forward footprint compatibility means, a board is designed to Crystal oscillator interface which can also be overdriven a accommodate the crystal oscillator interface, and the optional single-ended or differential reference clock control pins are also fully compatible with a canned oscillator Output frequency range: 83.33MHz 213.33MHz footprint (the canned oscillator will drop onto the 10-VFQFN footprint Crystal/Input frequency range: 15.625MHz 32MHz for second sourcing purposes). This capability provides designers with programability and lead time advantages of silicon/crystal based VCO range: 500MHz 640MHz solutions, while maintaining compatibility with industry standard PCI Express (2.5Gb/s) and Gen 2 (5 Gb/s) jitter compliant 5mm x 7mm oscillator footprints for ease of supply chain Cycle-to-cycle jitter: 45ps (maximum) management. Oscillator-level performance is maintained with IDTs rd 3 generation FemtoClock PLL technology, which delivers sub 1ps RMS phase jitter 125MHz, 1.875MHz 20MHz: 0.47ps (typical) RMS phase jitter. Full 3.3V or 2.5V operating supply The 83PR226I-01 defaults to 125MHz using a 25MHz crystal with all 4 of the programming pins floating (pulled HIGH with internal pullup -40C to 85C ambient operating temperature resistors), but can be also be set to 15 different frequency multiplier Available in lead-free (RoHS 6) packages settings to support a wide variety of applications. The table below shows some of the more common application settings. Common Applications and Settings (not exhaustive) XTAL Output Freq M1 M0 N1 N0 (MHz) (MHz) Application(s) Pin Assignments 0 0 1 0 19.44 155.52 SONET 0 0 1 0 19.2 153.6 W-CDMA 10 9 0 0 1 1 19.2 122.8 W-CDMA M1 1 8 VCC 0 1 0 0 26.5625 106.25 1G, 2G Fibre Channel M0 nQ 2 7 0 1 0 1 26.5625 212.5 2G, 4G Fibre Channel 1 0 0 1 25 166.66 Processor, PCI-X VEE 3 6 Q 45 1 1 0 0 24 100 Processor, PCI Express 1 1 1 0 1 24 200 Processor, PCI Express 2 1 1 0 1 22.5 187.5 12G Ethernet 83PR226I-01 1 1 1 0 25 156.25 10 Gb Ethernet 10-VFQFN 1 1 1 1 25 125 1 Gb Ethernet (default) 5mm x 7mm x 1mm package body K Package Top View 2017 Integrated Device Technology, Inc. 1 October 6, 2017 XTAL IN XTAL OUT83PR226I-01 Datasheet Block Diagram Pullup N0 Pullup N1 Output Divider Q XTAL IN N 1:0 Value OSC Phase Detector FemtoClock VCO 00 6 500MHz 640MHz 01 3 nQ 10 4 XTAL OUT 11 5 (default) M1 M0 M Value 0 0 32 0 1 24 1 0 20 1 1 25 (default) Pullup M1 Pullup M0 Table 1. Pin Descriptions Number Name Type Description Feedback divider control inputs. Sets the feedback divider value to one of four 1, 2 M1, M0 Input Pullup values: 32, 25, 24, or 20 (see Table 3A). LVCMOS/LVTTL interface levels. 3V Power Negative supply pin. EE Crystal oscillator interface XTAL IN is the input, XTAL OUT is the output. This XTAL IN 4, 5 Input oscillator interface can also be driven by a single-ended or differential reference XTAL OUT clock. 6, 7 Q, nQ Output Differential output pair. LVPECL interface levels. 8V Power Power supply pin. CC Output divider control inputs. Sets the output divider value to one of four values: 9, 10 N1, N0 Input Pullup 3, 4, 5, or 6 (see Table 3B). LVCMOS/LVTTL interface levels. NOTE: Pullup refers to internal input resistors. See Table 2, Pin Characteristics, for typical values. Table 2. Pin Characteristics Symbol Parameter Test Conditions Minimum Typical Maximum Units C Input Capacitance 3.5 pF IN R Input Pullup Resistor 51 k PULLUP 2017 Integrated Device Technology, Inc. 2 October 6, 2017