Femtoclocks Crystal-to-LVCMOS/LVTTL 840001I-34 Frequency Synthesizer Data Sheet General Description Features The 840001I-34 is a two output LVCMOS/LVTTL Synthesizer. One Two LVCMOS/LVTTL outputs, 22 typical output impedance One main clock output (Q) output is the LVCMOS/LVTTL main synthesized clock output (Q) One three-state reference clock output (REF OUT) and one output is a three-state LVCMOS/LVTTL reference clock Crystal oscillator interface can accept crystals from (REF OUT) output at the frequency of the crystal oscillator. The 15.3125MHz to 42.67MHz, 18pF parallel resonant crystal device can accept crystals from 15.3125MHz to 42.67MHz and can synthesize outputs from 81.67MHz to 213.33MHz. The Q output frequency range: 81.67MHz to 213.33MHz 840001I-34 is packaged in a 3mm x 3mm 16-pin VFQFN, making RMS phase jitter 106.25, (637kHz 10MHz): 0.38ps (typical) it ideal for use on space constrained boards. VCO range: 490MHz to 640MHz Full 3.3V and 2.5V operating supply -40C to 85C ambient operating temperature Available in lead-free (RoHS 6) package Common Application Configuration Table Inputs Output Frequency Crystal (MHz) M Divider VCO (MHz) N Divider (MHz) Application Serial Attached (SCSI), 40 15 600 6 100 (default) PCI Express, Processor Clock 26.5625 24 637.5 6 106.25 Fibre Channel 40 15 600 4 150 Serial ATA (SATA), Processor Clock 26.5625 24 637.5 3 212.5 Fibre Channel 2 25 25 625 5 125 Ethernet 25 25 625 4 156.25 10 Gigabit Ethernet 22.5 25 562.5 3 187.5 12 Gigabit Ethernet 19.44 32 622.08 4 155.52 SONET Block Diagram (Pullup) OE Pin Assignment REF OUT N-Div XTAL IN VCO 00 = 3 Phase Q OSC 01 = 4 Detector 490MHz - 640MHz 16 15 14 13 XTAL OUT 10 = 5 1 OE 12 Q 11 = 6 (default) XTAL IN 2 11 VDDO M-Div XTAL OUT 3 10 GND 11 = 15 (default) 10 = 24 M0 4 9 VDD 5 6 7 8 01 = 25 00 = 32 (Pullup) M1 840001-34 (Pullup) M0 16 Lead VFQFN (Pullup) 3mm x 3mm x 0.925 package body N1 (Pullup) N0 K Package Top View 2016 Integrated Device Technology, Inc 1 Revision A January 15, 2016 M1 VDDA nc nc N0 nc N1 REF OUT840001I-34 Data Sheet Table 1. Pin Descriptions Number Name Type Description Output enable pin. When HIGH, REF OUT output is enabled. When LOW, 1 OE Input Pullup forces REF OUT to Hi-Z state. See Table 3A. LVCMOS/LVTTL interface levels. 2, XTAL IN, Input Crystal oscillator interface. XTAL IN is the input. XTAL OUT is the output. 3 XTAL OUT 4, 5 M0, M1 Input Pullup M divider inputs. LVCMOS/LVTTL interface levels. See Table 3B. 6, 14, 15 nc Unused No connect. Determines output divider value as defined in Table 3C. 7, 8 No, N1 Input Pullup LVCMOS/LVTTL interface levels. 9V Power Core supply pin. DD 10 GND Power Power supply ground. 11 V Power Output supply pin. DDO Single-ended clock output. 22 typical output impedance. 12 Q Output LVCMOS/LVTTL interface levels. Single-ended three-state reference clock output. 22 typical output impedance. 13 REF OUT Output LVCMOS/LVTTL interface levels. 16 V Power Analog supply pin. DDA NOTE: Pullup refers to internal input resistors. See Table 2, Pin Characteristics, for typical values. Table 2. Pin Characteristics Symbol Parameter Test Conditions Minimum Typical Maximum Units C Input Capacitance 4pF IN V V = 3.465V 8 pF DD, DDO C Power Dissipation Capacitance PD V V = 2.625V 6 pF DD, DDO R Input Pullup Resistor 51 k PULLUP V V = 3.3V5% 14 22 30 DD, DDO R Output Impedance OUT V V = 2.5V5% 16 26 36 DD, DDO 2016 Integrated Device Technology, Inc 2 Revision A January 15, 2016