FemtoClocks Crystal-to-LVCMOS/ 840004 LVTTL Frequency Synthesizer DATASHEET GENERAL DESCRIPTION FEATURES The 840004 is a 4 output LVCMOS/LVTTL Synthesizer optimized Four LVCMOS/LVTTL outputs, 17 typical output impedance to generate Ethernet reference clock frequencies and is a member Selectable crystal oscillator interface TM of the HiPerClocks family of high performance clock solutions or LVCMOS single-ended input from IDT. Using a 26.5625MHz, 18pF parallel resonant crystal, the Supports the following input frequencies: 212.5MHz, following frequencies can be generated based on the 2 frequency 159.375MHz, 156.25MHz, 106.25MHz and 53.125MHz select pins (F SEL1:0): 212.5MHz, 159.375MHz, 156.25MHz, rd VCO range: 560MHz - 700MHz 106.25MHz, and 53.125MHz. The 840004 uses IDTs 3 generation low phase noise VCO technology and can achieve 1ps or lower RMS phase jitter 212.5MHz (637kHz - 10MHz): typical random rms phase jitter, easily meeting Ethernet jitter 0.49ps typical, V = 3.3V DDO requirements. The 840004 is packaged in a small 20-pin TSSOP Phase noise: package. Offset Noise Power 100Hz ................-88.8 dBc/Hz 1kHz ..............-109.0 dBc/Hz 10kHz ..............-116.1 dBc/Hz 100kHz ..............-117.5 dBc/Hz Full 3.3V or mixed 3.3V core/2.5V output supply mode 0C to 70C ambient operating temperature Available in lead-free (RoHS 6) package FREQUENCY SELECT FUNCTION TABLE Inputs Output Frequency Input Frequency M Divider N Divider M/N Ratio Range (MHz) F SEL1 F SEL0 (MHz) Value Value Value 26.5625 0 0 24 3 8 212.5 26.5625 0 1 24 4 6 159.375 26.5625 1 0 24 6 4 106.25 26.5625 1 1 24 12 2 53.125 (default) 26.04166 0 1 24 4 6 156.25 BLOCK DIAGRAM PIN ASSIGNMENT Pullup OE 20 F SEL0 1 F SEL1 2 Pullup:Pullup F SEL1:0 nc 2 19 GND 3 18 Q0 nXTAL SEL Pulldown nPLL SEL REF CLK 4 17 Q1 Pulldown OE 5 16 VDDO nXTAL SEL 15 MR 6 Q2 26.5625MHz nPLL SEL 7 14 Q3 XTAL IN 8 13 GND VDDA F SEL1:0 0 Q0 OSC nc 9 12 XTAL IN 1 N VDD 10 11 XTAL OUT 0 0 3 XTAL OUT 0 1 4 Q1 Phase Pulldown 1 REF CLK VCO 840004 0 Detector 1 0 6 20-Lead TSSOP 1 1 12 (default) Q2 6.5mm x 4.4mm x 0.92mm package body M = 24 (fixed) Q3 G Package Top View Pulldown MR 840004 REVISION B 4/1/15 1 2015 Integrated Device Technology, Inc.840004 DATA SHEET TABLE 1. PIN DESCRIPTIONS Number Name Type Description 1 F SEL0 Input Pullup Frequency select pin. LVCMOS/LVTTL interface levels. 2, 9 nc Unused No connect. Selects between the crystal or REF CLK inputs as the PLL reference 3 nXTAL SEL Input Pulldown source. When HIGH, selects REF CLK. When LOW, selects XTAL inputs. LVCMOS/LVTTL interface levels. 4 REF CLK Input Pulldown Single-ended LVCMOS/LVTTL reference clock input. Output enable pin. When HIGH, the outputs are active. When LOW, the 5 OE Input Pullup outputs are in a high impedance state. LVCMOS/LVTTL interface levels. Active HIGH Master Reset. When logic HIGH, the internal dividers are 6 MR Input Pulldown reset causing the otuputs to go low. When logic LOW, the internal dividers and the outputs are enabled. LVCMOS/LVTTL interface levels. PLL Bypass. When LOW, the output is driven from the VCO output. When HIGH, the PLL is bypassed and the output frequency = reference 7 nPLL SEL Input Pulldown clock frequency/N output divider. LVCMOS/LVTTL interface levels. 8V Power Analog supply pin. DDA 10 V Power Core supply pin. DD 11, XTAL OUT, Crystal oscillator interface. XTAL OUT is the output. Input 12 XTAL IN XTAL IN is the input. 13, 19 GND Power Power supply ground. 14, 15 17, Q3, Q2, Single-ended clock outputs. LVCMOS/LVTTL interface levels. Output 18 Q1, Q0 17 typical output impedance. 16 V Power Output supply pin. DDO 20 F SEL1 Input Pullup Frequency select pin. LVCMOS/LVTTL interface levels. NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values. TABLE 2. PIN CHARACTERISTICS Symbol Parameter Test Conditions Minimum Typical Maximum Units C Input Capacitance 4 pF IN C Power Dissipation Capacitance 8 pF PD R Input Pullup Resistor 51 k PULLUP R Input Pulldown Resistor 51 k PULLDOWN V = 3.3V5% 17 DDO R Output Impedance OUT V = 2.5V5% 21 DDO FEMTOCLOCKS CRYSTAL-TO-LVCMOS/ 2 REVISION B 4/1/15 LVTTL FREQUENCY SYNTHESIZER