Crystal-to-LVCMOS/LVTTL Frequency 840S07I Synthesizer Data Sheet General Description Features The 840S07I is a seven output LVCMOS/LVTTL Frequency Five single-ended LVCMOS/LVTTL outputs Synthesizer accepting crystal or single-ended reference clock Two REF OUT LVCMOS/LVTTL clock outputs inputs. The 840S07I uses a 25MHz parallel resonant crystal to Selectable crystal oscillator interface, 25MHz, 18pF parallel generate 33.33MHz 166.67MHz clock signals, replacing solutions resonant crystal or LVCMOS/LVTTL single-ended reference input requiring multiple oscillator and fanout buffer solutions. The device Supports the following output frequencies: supports output slew rate control with two slew select pins Output QAA/Bank B: 33.33MHz, 50MHz, 66.67MHz, 83.33MHz, (SLEW 1:0 ). The VCO operates at a frequency of 2GHz. The device 100MHz, 125MHz, 133.33MHz and 166.67MHz has 3 output banks, output QAA with one 33.33MHz 166.67MHz Output QAB: 125MHz LVCMOS/LVTTL output, output QAB with one 125MHz VCO frequency: 2GHz LVCMOS/LVTTL output and Bank B with three 33.33MHz Slew rate control 166.67MHz LVCMOS/LVTTL outputs. Voltage supply modes: Output QAA and Bank B have their own dedicated frequency select Core/Output pins and can be independently set for the frequencies mentioned 3.3V/3.3V above. Designed for networking and industrial applications, the 3.3V/2.5V 840S07I can also drive the high-speed clock inputs of -40C to 85C ambient operating temperature communication processors, DSPs, switches and bridges. Available in lead-free (RoHS 6) package Pin Assignment 3 2, 1 Pulldown, 0 Pullup F SELAA 2:0 Block Diagram QAA NAA 32 31 30 29 28 27 26 25 VDDA 1 GND 24 XTAL IN 125MHz 0 25MHz OSC NAB QAB VDD 2 23 QAA 16 PLL XTAL OUT XTAL OUT 3 22 VDDO AA VCO GND 2GHz XTAL IN 4 21 Pulldown REF IN GND 5 QB0 1 20 QB0 25MHz REF SEL 6 19 QB1 Pulldown REF SEL REF IN 7 QB2 18 M = 80 QB1 NB F SELB2 8 VDDO B 17 9 10 11 12 13 14 15 16 QB2 2 Pulldown SLEW 1:0 Pulldown MR/nOE REF OUT0 840S07I 3 Pulldown F SELB 2:0 32-Lead TQFP, E-Pad REF OUT1 7mm x 7mm x1mm package body Pullup nOE REF Y Package Top View 2016 Integrated Device Technology, Inc 1 Revision A April 14, 2016 nOE REF F SELAA2 VDDO REF SLEW1 REF OUT0 SLEW0 REF OUT1 F SELAA1 F SELAA0 GND F SELB1 GND MR/nOE QAB F SELB0 VDDO AB840S07I Data Sheet Table 1. Pin Descriptions Number Name Type Description 1V Power Analog supply pin. DDA 2V Power Core supply pin. DD 3, XTAL OUT, Input Crystal oscillator interface. XTAL IN is the input. XTAL OUT is the output. 4 XTAL IN 5, 13, GND Power Power supply ground. 21, 24, 27 Reference select pin. When HIGH selects REF IN. When LOW, selects 6 REF SEL Input Pulldown crystal. See Table 3D. LVCMOS/LVTTL interface levels. Single-ended reference clock input. Table 3B. 7 REF IN Input Pulldown LVCMOS/LVTTL interface levels. 8, F SELB2, Frequency select pins for Bank B outputs. See Table 3C. 14, F SELB1, Input Pulldown LVCMOS/LVTTL interface levels. 16 F SELB0 Active low REF OUT enable/disable pin. See Table 3F. 9 nOE REF Input Pullup LVCMOS/LVTTL interface levels. 10 V Power Output supply pin for REF OUTx clock outputs. DDO REF 11, REF OUT0, Output Single-ended reference clock outputs. LVCMOS/LVTTL interface levels. 12 REF OUT1 Active HIGH Master Reset. Active LOW output enable. When logic HIGH, the internal dividers are reset and the outputs are in high impedance (HI-Z). 15 MR/nOE Input Pulldown When logic LOW, the internal dividers and the outputs are enabled. See Table 3E. LVCMOS/LVTTL interface levels. 17 V Power Output supply pin for QBx outputs. DDO B 18, 19, 20 QB2, QB1, QB0 Output Single-ended Bank QBx clock outputs. LVCMOS/ LVTTL interface levels. 22 V Power Output supply pin for QAA output. DDO AA 23 QAA Output Single-ended QAA clock output. LVCMOS/LVTTL interface levels. 25 V Power Output supply pin for QAB output. DDO AB 26 QAB Output Single-ended QAB clock output. LVCMOS/LVTTL interface levels. Frequency select pin for QAA output. See Table 3A. 28 F SELAA0 Input Pullup LVCMOS/LVTTL interface levels. 29, F SELAA1, Frequency select pins for QAA output. See Table 3A. Input Pulldown 32 F SELAA2 LVCMOS/LVTTL interface levels. Slew rate select pins for LVCMOS/LVTTL clock output. 30, 31 SLEW0, SLEW1 Input Pulldown LVCMOS/LVTTL interface levels. NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values. 2016 Integrated Device Technology, Inc 2 Revision A April 14, 2016