nQ4 FSEL IREF Q4 VDD BYPASS nQ3 VDDA Q3 REF SEL nQ2 REF IN Q2 VDD GND GND FemtoClock Crystal-to-HCSL 841608 Clock Generator Datasheet General Description Features The 841608 is an optimized PCIe and sRIO clock generator. The Eight HCSL outputs: configurable for PCIe (100MHz) and sRIO (125MHz) clock signals device uses a 25MHz parallel crystal to generate 100MHz and 125MHz clock signals, replacing solutions requiring multiple Selectable crystal oscillator interface, 25MHz, 18pF parallel resonant crystal or LVCMOS/LVTTL single-ended reference clock oscillator and fanout buffer solutions. The device has excellent input phase jitter (< 1ps rms) suitable to clock components requiring precise and low-jitter PCIe or sRIO or both clock signals. Designed Supports the following output frequencies: 100MHz or 125MHz for telecom, networking and industrial applications, the 841608 can VCO: 500MHz also drive the high-speed sRIO and PCIe SerDes clock inputs of PLL bypass and output enable communication processors, DSPs, switches and bridges. PCI Express (2.5 Gb/S) and Gen 2 (5 Gb/s) jitter compliant RMS phase jitter at 125MHz, using a 25MHz crystal (1.875MHz 20MHz): 0.37ps (typical) Full 3.3V operating supply -40C to 85C ambient operating temperature Available in lead-free (RoHS 6) package Block Diagram Pin Assignment XTAL IN Q0 1 0 OSC nQ0 FemtoClock XTAL OUT N PLL 0 Pulldown VCO = 500MHz 4 Q1 REF IN 32 31 30 29 28 27 26 25 1 5 (default) nQ1 XTAL IN 1 24 VDD Pulldown REF SEL XTAL OUT 2 23 nQ7 Q2 MR/nOE 3 22 Q7 M = 20 VDD 4 21 nQ6 nQ2 IREF Q0 5 20 Q6 Q3 nQ0 6 19 GND Pulldown BYPASS Q1 7 18 nQ5 nQ3 Pulldown FSEL nQ1 8 17 Q5 Q4 9 10 11 12 13 14 15 16 nQ4 Q5 841608 nQ5 32-Lead VFQFPN 5mm x 5mm x 0.925mm package body Q6 K Package nQ6 Top View Q7 nQ7 Pulldown MR/nOE 2020 Renesas Electronics Corporation 1 March 9, 2020841608 Datasheet Pin Description and Pin Characteristic Tables Table 1. Pin Descriptions Number Name Type Description 1, XTAL IN, Parallel resonant crystal interface. XTAL OUT is the output, Input 2 XTAL OUT XTAL IN is the input. Active HIGH master reset. Active LOW output enable. When logic HIGH, the internal dividers are reset and the outputs are in high impedance (Hi-Z). 3 MR/nOE Input Pulldown When logic LOW, the internal dividers and the outputs are enabled. Asynchronous function. LVCMOS/LVTTL interface levels. See Table 3D. 4, 14, 24, 31 V Power Core supply pins. DD 5, 6 Q0, nQ0 Output Differential output pair. HCSL interface levels. 7, 8 Q1, nQ1 Output Differential output pair. HCSL interface levels. 9, 19, 32 GND Power Power supply ground. 10, 11 Q2, nQ2 Output Differential output pair. HCSL interface levels. 12,13 Q3, nQ3 Output Differential output pair. HCSL interface levels. 15, 16 Q4, nQ4 Output Differential output pair. HCSL interface levels. 17, 18 Q5, nQ5 Output Differential output pair. HCSL interface levels. 20, 21 Q6, nQ6 Output Differential output pair. HCSL interface levels. 22, 23 Q7, nQ7 Output Differential output pair. HCSL interface levels. 25 FSEL Input Pulldown Output frequency select pin. LVCMOS/LVTTL interface levels. See Table 3B. HCSL current reference resistor output. An external fixed precision resistor ) from this pin to ground provides a reference current used for differential 26 IREF Output (475 current-mode Qx, nQx clock outputs. Selects PLL operation/PLL bypass operation. Asynchronous function. 27 BYPASS Input Pulldown LVCMOS/LVTTL interface levels. See Table 3C. 28 V Power Analog supply pin. DDA Reference select. Selects the input reference source. 29 REF SEL Input Pulldown LVCMOS/LVTTL interface levels. See Table 3A. 30 REF IN Input Pulldown LVCMOS/LVTTL PLL reference clock input. NOTE: Pulldown refers to internal input resistors. See Table 2, Pin Characteristics, for typical values. Table 2. Pin Characteristics Symbol Parameter Test Conditions Minimum Typical Maximum Units Input Capacitance 4 pF C IN R Input Pulldown Resistor 51 k PULLDOWN 2020 Renesas Electronics Corporation 2 March 9, 2020