FemtoClock NG Crystal-to-HCSL 841N4830 Frequency Synthesizer Datasheet General Description Features The 841N4830 is a 3 HCSL, 1 LVPECL and 2 LVCMOS output Fourth generation FemtoClock Next Generation (NG) technology Synthesizer optimized to generate PCI Express reference clock Three differential HCSL outputs, one differential LVPECL and frequencies. The device uses IDTs fourth generation FemtoClock two single-ended LVCMOS/LVTTL outputs NG technology for synthesis of high clock frequency at very low Crystal oscillator interface designed for a 25MHz, 12pF parallel phase noise. It provides low power consumption with good power resonant crystal supply noise rejection. Using a 25MHz, 12pF parallel resonant CLK/nCLK input pair can accept the following differential input crystal, the following frequencies can be generated: 100MHz, levels: LVPECL, LVDS, HCSL 50MHz and 25MHz. Maximum rms phase jitter of 0.36ps, easily A 25MHz crystal generates output frequencies of: 100MHz, meets PCI Express jitter requirements. The 841N4830 is packaged 50MHz and 25MHz in a small 32-pin VFQFN package. VCO frequency: 2GHz RMS Phase Jitter 100MHz, (12kHz 20MHz) using a 25MHz crystal: 0.36ps (maximum) Power supply noise rejection PSNR: -45dB (typical) PCI Express Gen 2 (5 Gb/s) jitter compliant Full 3.3V supply mode -40C to 85C ambient operating temperature Available in lead-free (RoHS 6) package Block Diagram Pin Assignment Pulldown nOE REF 25MHz LVPECL REF OUT 32 31 30 29 28 27 26 25 nREF OUT Pulldown PLL BYPASS 1 PLL BYPASS 24 QA1 Pulldown nOEA 2 nOE REF 23 nQA1 841N4830 25MHz nOEB 3 32-Lead VFQFN 22 VDDO XTAL IN 100MHz HCSL 1 5mm x 5mm x 0.925mm DIV2 QB 4 21 QA2 0 3 OSC QA 2:0 PFD FemtoClock NG package body V DDA 5 20 nQA2 20 3 XTAL OUT & VCO nQA 2:0 K Package 2GHz LPF 0 6 CLK 19 GND Pulldown Top View CLK 100MHz LVCMOS 7 QA3 1 nCLK 18 Pullup nCLK QA3 V DDO REF 8 VDDO QA3 17 Pullup CLK SEL 9 10 11 12 13 14 15 16 1 0 IREF 100/50MHz LVCMOS QB 1 2 80 Pullup DIV2 QB Pulldown nOEB 2016 Integrated Device Technology, Inc. 1 Revision F, May 23, 2016 REF OUT VDDA nREF OUT VDD CLK SEL nOEA VDDO XTAL IN XTAL OUT IREF VDD OSC QA0 VDDO QB nQA0 QB GND841N4830 Datasheet Pin Description and Pin Characteristic Tables Table 1. Pin Descriptions Number Name Type Description When HIGH, PLL is bypassed and outputs are driven by input crystal or clock. When 1 PLL BYPASS Input Pulldown LOW outputs are driven by PLL. LVCMOS/LVTTL interface levels. See Table 3D. Output enable signal for REF OUT output. When LOW, outputs are enabled. 2 nOE REF Input Pulldown LVCMOS/LVTTL interface levels. See Table 3C. Output enable signal for Bank B. When LOW, QB output is enabled. When HIGH, 3 nOEB Input Pulldown selects high impedance mode. LVCMOS/LVTTL interface levels.See Table 3B. Select signal for the output divider for Bank B. LVCMOS/LVTTL clock output. See 4 DIV2 QB Input Pullup Table 3F. 5, 32 V Power Analog supply pins. DDA 6 CLK Input Pulldown Non-inverting differential clock input. 7 nCLK Input Pullup Inverting differential clock input. 8V Power Output power supply pin for LVPECL reference outputs. DDO REF REF OUT, 9, 10 Output 25MHz differential reference output pair. LVPECL interface levels. nREF OUT Input select signal. When HIGH, selects CLK, nCLK inputs. When LOW, selects XTAL 11 CLK SEL Input Pullup inputs. LVCMOS/LVTTL interface levels.See Table 3E. 12 XTAL IN Input Crystal oscillator interface XTAL IN is the input, XTAL OUT is the output. 13 XTAL OUT 14 V Power Core supply pin for crystal oscillator. DD OSC Power Output power supply pin for Bank B LVCMOS output. 15 V DDO QB 16 QB Output Single-ended output. LVCMOS/LVTTL interface levels. 17 V Power Output power supply pin for QA3 LVCMOS output. DDO QA3 18 QA3 Output Single-ended output. LVCMOS/LVTTL interface levels. 19, 25 GND Power Power supply ground. 20, 21 nQA2, QA2 Output 100MHz differential output pair. HCSL interface levels. Power Output power supply pins for Bank A HCSL outputs. 22, 29 V DDO 23, 24 nQA1, QA1 Output 100MHz differential output pair. HCSL interface levels. 26, 27 nQA0, QA0 Output 100MHz differential output pair. HCSL interface levels. 0.7V current reference resistor output. An external fixed precision resistor (475 ) from 28 IREF this pin to ground provides a reference current used for differential current-mode QAx, nQAx clock outputs. Output Enable signal for Bank A. When LOW enables output. When HIGH selects 30 nOEA InputPulldown high impedance mode. LVCMOS/LVTTL interface levels.See Table 3A. 31 V Power Core supply pin. DD NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values. 2016 Integrated Device Technology, Inc. 2 Revision F, May 23, 2016