Crystal-to-0.7V Differential HCSL/ 841S012DI Datasheet LVCMOS Frequency Synthesizer GENERAL DESCRIPTION FEATURES The 841S012DI is an optimized PCIe, sRIO and Gigabit Ethernet Two 0.7V differential HCSL outputs (Bank A), con gurable for Frequency Synthesizer and a member of high performance clock PCIe (100MHz or 250MHz) and sRIO (100MHz or 125MHz) solutions from IDT. The 841S012DI uses a 25MHz parallel resonant clock signals crystal to generate 33.33MHz - 200MHz clock signals, replacing Eight LVCMOS/LVTTL outputs (Banks B/C), multiple oscillators and fanout buffer solutions. The device supports 18 typical output impedance 0.25% center-spread, and -0.5% down-spread clocking with two Two REF OUT LVCMOS/LVTTL clock outputs, spread select pins (SSC 1:0 ). The VCO operates at a frequency of 23 typical output impedance 2GHz. The device has three output banks: Bank A with two 100MHz 250MHz HCSL outputs Bank B with seven 33.33MHz 200MHz Selectable crystal oscillator interface, 25MHz, 18pF parallel LVCMOS/ LVTTL outputs and Bank C with one 33.33MHz 200MHz resonant crystal or one LVCMOS/LVTTL single-ended refer- LVCMOS/LVTTL output. ence clock input Supports the following output frequencies: All Banks A, B and C have their own dedicated frequency HCSL Bank A: 100MHz, 125MHz, 200MHz and 250MHz select pins and can be independently set for the frequencies LVCMOS/LVTTL Bank B/C: 33.33MHz, 50MHz, 66.67MHz, mentioned above. The low jitter characteristic of the 841S012DI 100MHz, 125MHz, 133.33MHz, 166.67MHz and 200MHz makes it an ideal clock source for PCIe, sRIO and Gigabit Ethernet applications. Designed for networking and industrial applications, VCO: 2GHz the 841S012DI can also drive the high-speed clock inputs of com- Spread spectrum clock: 0.25% center-spread (typical) and munication processors, DSPs, switches and bridges. -0.6% down-spread (typical) PLL bypass and output enable RMS period jitter: 10ps (typical), QAx/nQAx outputs Full 3.3V supply mode -40C to 85C ambient operating temperature Available in lead-free (RoHS 6) package PIN ASSIGNMENT 56 55 54 53 52 51 50 49 48 47 46 45 44 43 V 1 42 V DD REFOUT DDOC REF OUT0 2 41 QC 3 GND REF OUT1 40 GND 4 39 QBC OE ICS841S012DI GND 5 38 V DDA 56-Lead VFQFN 6 V REF IN 37 DDA V 7 36 GND DD 8mm x 8mm x 0.925mm REF SEL 8 GND 35 package body XTAL IN 9 IREF 34 K Package XTAL OUT 10 33 QA0 BYPASS 11 Top View 32 nQA0 12 QA1 REF OE 31 nMR 13 30 nQA1 V DD 14 29 V DD 15 16 17 18 19 20 21 22 23 24 25 26 27 28 2016 Integrated Device Technology, Inc 1 January 4, 2016 GND VDDOB SSC1 QB6 SSC0 GND F SELB2 QB5 F SELB1 VDDOB F SELB0 QB4 F SELC2 GND F SELC1 QB3 F SELC0 VDDOB QB2 F SELA1 GND F SELA0 QA OE QB1 GND QB0 VDD VDDOB841S012DI Datasheet BLOCK DIAGRAM Pullup QA OE 2 Pulldown F SELA 1:0 QA0 Pulldown nQA0 BYPASS NA QA1 25MHz XTAL IN nQA1 1 OSC 0 XTAL OUT PLL QB0 VCO 2GHz 0 Pulldown REF IN 1 QB1 Pulldown REF SEL QB2 M = 80 QB3 NB QB4 3 Pulldown F SELB 2:0 QB5 IREF QB6 QC NC 3 Pulldown F SELC 2:0 Pullup nMR Pullup QBC OE Pullup 2 Spread SSC 1:0 Spectrum REF OUT0 REF OUT1 Pulldown REF OE 2016 Integrated Device Technology, Inc 2 January 4, 2016