VDD Crystal-to-HSTL, 100MHz/ 200MHz 842S104E PCI Express Clock Synthesizer Datasheet General Description Features The 842S104E is a PLL-based clock generator specifically designed Four differential HSTL output pairs for PCI Express Clock Generation 2 applications. This device Crystal oscillator interface: 25MHz generates either a 200MHz or 100MHz differential HSTL clock from Output frequency: 100MHz or 200MHz an input reference of 25MHz. The input reference may be derived RMS phase jitter 200MHz (12kHz 20MHz): 1.229ps (typical) from an external source or by the addition of a 25MHz crystal to the on-chip crystal oscillator. An external reference is applied to the Cycle-to-cycle jitter: 25ps (maximum) XTAL IN pin with the XTAL OUT pin left floating.The device offers 2 I C support with readback capabilities up to 400kHz 2 spread spectrum clock output for reduced EMI applications. An I C Spread Spectrum for electromagnetic interference (EMI) reduction bus interface is used to enable or disable spread spectrum operation 3.3V core/1.5V to 2.0V output operating supply as well as select either a down spread value of -0.35% or -0.5%.The 842S104E is available in a lead-free 24-Lead package. 0C to 70C ambient operating temperature Available lead-free (RoHS 6) package PCI Express Gen2 Jitter Compliant HiPerClockS Block Diagram Pin Assignment SRCC4 SRCT3 1 24 25MHz 4 SRCT 1:4 XTAL IN SRCC3 2 23 SRCT4 Divider OSC PLL 4 V SS 3 22 VDDO Network SRCC 1:4 XTAL OUT V 4 21 SDATA DDO SRCT2 5 20 SCLK Pullup SRCC2 6 19 XTAL OUT SDATA 2 SRCT1 7 18 XTAL IN I C Pullup SCLK Logic SRCC1 8 17 V SS 9 16 VSS V nc DD 10 15 V SS 11 14 VDDA 12 13 VSS nc 842S104E 24-Lead TSSOP 4.4mm x 7.8mm x 0.925mm package body G Package Top View 2016 Integrated Device Technology, Inc 1 January 4, 2016842S104E Datasheet Pin Description and Pin Characteristics Tables Table 1. Pin Descriptions Number Name Type Description 1, 2 SRCT3, SRCC3 Output Differential output pair. HSTL interface levels. 3, 9, V Power Power supply ground. SS 11, 13, 16 4, 22 V Power Output power supply pins. DDO 5, 6 SRCT2, SRCC2 Output Differential output pair. HSTL interface levels. 7, 8 SRCT1, SRCC1 Output Differential output pair. HSTL interface levels. 10, 17 V Power Core supply pins. DD 12, 15 nc Unused No connect. 14 V Power Analog supply for PLL. DDA 18, 19 XTAL IN, XTAL OUT Input Crystal oscillator interface. XTAL IN is the input. XTAL OUT is the output. 2 I C compatible SCLK. This pin has an internal pullup resistor. 20 SCLK Input Pullup LVCMOS/LVTTL interface levels. 2 I C compatible SDATA. This pin has an internal pullup resistor. Open drain. 21 SDATA I/O Pullup LVCMOS/LVTTL interface levels. 23, 24 SRCT4, SRCC4 Output Differential output pair. HSTL interface levels. NOTE: Pullup refers to internal input resistors. See Table 2, Pin Characteristics, for typical values. Table 2. Pin Characteristics Symbol Parameter Test Conditions Minimum Typical Maximum Units C Input Capacitance 2pF IN R Input Pullup Resistor 51 k PULLUP 2016 Integrated Device Technology, Inc 2 January 4, 2016