SEL1 XTAL OUT0 FemtoClock 843001I-23 Crystal/LVCMOS-to-LVPECL/ LVCMOS Frequency Synthesizer DATA SHEET General Description Features The 843001I-23 is a highly versatile, low phase noise One 3.3Vdifferential LVPECL output pair and one LVCMOS/LVTTL single-ended reference clock output LVPECL/LVCMOS Synthesizer which can generate low jitter reference clocks for a variety of communication applications. The Selectable crystal oscillator interface or LVCMOS/LVTTL single-ended input dual crystal interface allows the synthesizer to support up to three communication standards in a given application (i.e. SONET with a Crystal and CLK range: 19.44MHz 27MHz 19.44MHz crystal, 1Gb/10Gb Ethernet and Fibre Channel using a Able to generate GbE/10GbE/12GbE, Fibre Channel 25MHz crystal). The RMS phase jitter performance is typically less (1Gb/4Gb/10Gb), PCI-E and SATA from a 25MHz crystal than 1ps, thus making the device acceptable for use in demanding VCO range: 1.12GHz 1.275GHz applications such as OC48 SONET, GbE/10Gb Ethernet and SAN Supports the following applications: applications. The 843001I-23 is packaged in a small 24-pin TSSOP, SONET, Ethernet, Fibre Channel, Serial ATA, and HDTV E-Pad package. RMS phase jitter 622.08MHz (12kHz - 20MHz): 0.9ps (typical), 3.3V Supply modes V /V CC CCO 3.3V/3.3V 3.3V/2.5V 2.5V/2.5V -40C to 85C ambient operating temperature Available in lead-free (RoHS 6) package Block Diagram Pin Assignment 3 REF OUT V 1 24 CCO LVCMOS N2:N0 2 23 VEE N0 OE REF N1 3 22 Pulldown SEL0 N2 M2 4 21 M1 Pulldown V 5 20 CCO LVPECL SEL1 M0 Q 6 19 N MR nQ 7 18 XTAL IN0 V 8 17 EE 000 2 V 9 SEL0 CCA 16 001 4 OSC 00 11 CLK V 10 15 CC 010 5 Q XTAL OUT1 11 14 XTAL IN0 011 6 XTAL OUT0 XTAL IN1 12 13 10 nQ 100 8 (default) XTAL IN1 Phase 01 VCO 843001I-23 101 10 Detector 00 01 OSC 110 12 24-Lead TSSOP, E-Pad 111 16 4.4mm x 7.8mm x 0.925mm XTAL OUT1 M package body 000 44 10 Pulldown CLK 001 45 G Package 11 010 48 011 50 Top View 100 51 111 64 (default) Pulldown MR 3 Pullup M2:M0 REF OUT Pulldown OE REF 843001I-23 Rev A 11/17/15 1 2015 Integrated Device Technology, Inc.843001I-23 DATA SHEET Table 1. Pin Descriptions Number Name Type Description 1V Power Output supply pin for REF CLK output. CCO LVCMOS 2, 3 N0, N1 Input Pulldown Output divider select pins. LVCMOS/LVTTL interface levels. See Table 3C. 4 N2 Input Pullup 5V Power Output supply pin for LVPECL output. CCO LVPECL 6, 7 Q, nQ Output Differential output pair. LVPECL interface levels. 8, 23 V Power Negative supply pins. EE 9V Power Analog supply pin. CCA 10 V Power Core supply pin. CC 11, XTAL OUT1, Parallel resonant crystal interface. Input 12 XTAL IN1 XTAL OUT1 is the output, XTAL IN1 is the input. 13, XTAL OUT0, Parallel resonant crystal interface. Input 14 XTAL IN0 XTAL OUT0 is the output, XTAL IN0 is the input. 15 CLK Input Pulldown Single-ended clock input. LVCMOS/LVTTL interface levels. 16, 17 SEL0, SEL1 Input Pulldown Input MUX select pins. LVCMOS/LVTTL interface levels. See Table 3D. Active HIGH Master Reset. When logic HIGH, the internal dividers are reset causing the true output Q to go low and the inverted output nQ to go high. 18 MR Input Pulldown When logic LOW, the internal dividers and the outputs are enabled. LVCMOS/LVTTL interface levels. 19, 20, 21 M0, M1, M2 Input Pullup Feedback divider select pins. LVCMOS/LVTTL interface levels. See Table 3B. Reference clock output enable. Default LOW. See Table 3E. 22 OE REF Input Pulldown LVCMOS/LVTTL interface levels. 24 REF OUT Output Reference clock output. LVCMOS/LVTTL interface levels. NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values. Table 2. Pin Characteristics Symbol Parameter Test Conditions Minimum Typical Maximum Units C Input Capacitance 4pF IN Input Pullup Resistor 51 k R PULLUP R Input Pulldown Resistor 51 k PULLDOWN V = 3.3V 21 CCO R Output Impedance REF OUT OUT V = 2.5V 25 CCO Rev A 11/17/15 2 FEMTOCLOCK CRYSTAL/LVCMOS-TO-LVPECL/ LVCMOS FREQUENCY SYNTHESIZER