FemtoClock Crystal-to-3.3V LVPECL 843002-01 Frequency Synthesizer DATASHEET GENERAL DESCRIPTION FEATURES The 843002-01 is a 2 output LVPECL synthesizer optimized Two 3.3V LVPECL outputs to generate Ethernet reference clock frequencies. Using a Selectable crystal oscillator interface 25MHz 18pF parallel resonant crystal, the following frequencies or LVCMOS single-ended input can be generated based on the 2 frequency select pins (F SEL 1:0 ): 156.25MHz, 125MHz, and 62.5MHz. The 843002- Supports the following input frequencies: rd 01 uses ICS 3 generation low phase noise VCO technology 156.25MHz, 125MHz and 62.5MHz and can achieve 1ps or lower typical rms phase jitter, easily VCO range: 560MHz - 680MHz meeting Ethernet jitter requirements. The 843002-01 is packaged in a small 20-pin TSSOP package. RMS phase jitter 156.25MHz, using a 25MHz crystal (1.875MHz-20MHz): 0.54ps (typical) Typical phase noise at 156.25MHz Phase noise: Offset Noise Power 100Hz ................-97.3 dBc/Hz 1KHz ..............-119.1 dBc/Hz 10KHz ..............-126.4 dBc/Hz 100KHz ..............-127.6 dBc/Hz Full 3.3V supply mode Lead-Free package fully RoHS compliant -30C to 85C ambient operating temperature FREQUENCY SELECT FUNCTION TABLE PIN ASSIGNMENT Inputs nc 1 20 VCCO Output Frequency 2 19 Q1 M Divider N Divider VCCO (25MHz Ref.) F SEL1 F SEL0 Q0 3 18 nQ1 Value Value nQ0 4 17 VEE 0 0 25 4 156.25 16 MR 5 VCC nPLL SEL 6 15 nXTAL SEL 0 1 25 5 125 7 14 TEST CLK nc 1 0 25 10 62.5 VCCA 8 13 XTAL IN F SEL0 9 12 XTAL OUT 1 1 Not Used Not Used 11 VCC 10 F SEL1 843002-01 BLOCK DIAGRAM 20-Lead TSSOP Pulldown 6.5mm x 4.4mm x 0.92mm 2 F SEL 1:0 package body Q0 Pulldown G Package nPLL SEL F SEL 1:0 Top View nQO 0 0 4 0 1 5 1 0 10 Pulldown TEST CLK 11 1 1 not used Q1 1 25MHz nQ1 VCO XTAL IN Phase OSC 625MHz 0 0 Detector (w/25MHz XTAL OUT Reference) Pulldown nXTAL SEL M = 25 (fixed) Pulldown MR 843002-01 REVISION B 4/6/15 1 2015 Integrated Device Technology, Inc.843002-01 DATA SHEET TABLE 1. PIN DESCRIPTIONS Number Name Type Description 1, 7 nc Unused No connect. 2, 20 V Power Output supply pins. CCO 3, 4 Q0, nQ0 Ouput Differential output pair. LVPECL interface levels. Active HIGH Master Reset. When logic HIGH, the internal dividers are reset causing the true outputs Qx to go low and the inverted outputs nQx 5 MR Input Pulldown to go high. When logic LOW, the internal dividers and the outputs are en- abled. LVCMOS/LVTTL interface levels. Selects between the PLL and TEST CLK as input to the dividers. When 6 nPLL SEL Input Pulldown LOW, selects PLL (PLL Enable). When HIGH, deselects the reference clock (PLL Bypass). LVCMOS/LVTTL interface levels. 8V Power Analog supply pin. CCA F SEL0, 9, 11 Input Pulldown Frequency select pins. LVCMOS/LVTTL interface levels. F SEL1 10, 16 V Power Core supply pin. CC XTAL OUT, Parallel resonant crystal interface. XTAL OUT is the output, 12, 13 Input XTAL IN XTAL IN is the input. 14 TEST CLK Input Pulldown LVCMOS/LVTTL clock input. Selects between crystal or TEST CLK inputs as the the PLL Reference 15 nXTAL SEL Input Pulldown source. Selects XTAL inputs when LOW. Selects TEST CLK when HIGH. LVCMOS/LVTTL interface levels. 17 V Power Negative supply pins. EE 18, 19 nQ1, Q1 Output Differential output pair. LVPECL interface levels. 2, 20 V Power Output supply pins. CCO NOTE: Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values. TABLE 2. PIN CHARACTERISTICS Symbol Parameter Test Conditions Minimum Typical Maximum Units C Input Capacitance 4 pF IN R Input Pulldown Resistor 51 k PULLDOWN FemtoClock Crystal-to-3.3V LVPECL 2 REVISION B 4/6/15 Frequency Synthesizer