FemtoClocks Crystal-to- 843002I-01 3.3V, 2.5V LVPECL Frequency Synthesizer DATASHEET GENERAL DESCRIPTION FEATURES The 843002I-01 is a 2 output LVPECL synthesizer optimized to Two 3.3V or 2.5V LVPECL outputs generate Ethernet reference clock frequencies. Using a 25MHz Selectable crystal oscillator interface 18pF parallel resonant crystal, the following frequencies can be or LVCMOS/LVTTL single-ended input generated based on the 2 frequency select pins (F SEL 1:0 ): Supports the following output frequencies: 156.25MHz, 125MHz, and 62.5MHz. The 843002I-01 uses 156.25MHz, 125MHz and 62.5MHz IDTs FemtoClock low phase noise VCO technology and can achieve 1ps or lower typical rms phase jitter, easily meeting VCO range: 560MHz - 680MHz Ethernetjitter requirements. The 843002I-01 is packaged in a RMS phase jitter 156.25MHz, using a 25MHz crystal small 20-pin TSSOP package. (1.875MHz-20MHz): 0.55ps (typical) Output skew: 30ps (maximum) Supply Voltage Modes Core/Outputs 3.3/3.3 2.5/2.5 -40C to 85C ambient operating temperature Available in lead-free RoHS-compliant package FREQUENCY SELECT FUNCTION TABLE PIN ASSIGNMENT Inputs 1 20 nc VCCO Output Frequency VCCO 2 19 Q1 M Divider N Divider (25MHz Ref.) F SEL1 F SEL0 Q0 3 18 nQ1 Value Value nQ0 4 17 VEE 0 0 25 4 156.25 (default) MR 5 16 VCC 6 15 nPLL SEL nXTAL SEL 0 1 25 5 125 nc 7 14 REF CLK 1 0 25 10 62.5 VCCA 8 13 XTAL IN F SEL0 9 12 XTAL OUT 1 1 25 5 125 VCC 10 11 F SEL1 843002I-01 20-Lead TSSOP 6.5mm x 4.4mm x 0.92mm BLOCK DIAGRAM Pulldown package body F SEL 1:0 2 G Package Q0 Pulldown Top View nPLL SEL F SEL 1:0 nQ0 0 0 4 (default) 0 1 5 1 0 10 Pulldown REF CLK 11 Q1 1 1 5 1 nQ1 25MHz VCO XTAL IN Phase OSC 625MHz 0 0 (w/25MHz Detector Reference) XTAL OUT Pulldown nXTAL SEL M = 25 (fixed) Pulldown MR 843002I-01 REVISION A 2/20/15 1 2015 Integrated Device Technology, Inc.843002I-01 DATA SHEET TABLE 1. PIN DESCRIPTIONS Number Name Type Description 1, 7 nc Unused No connect. 2, 20 V Power Output supply pins. CCO 3, 4 Q0, nQ0 Ouput Differential output pair. LVPECL interface levels. Active HIGH Master Reset. When logic HIGH, the internal dividers are reset causing the true outputs Qx to go low and the inverted outputs nQx 5 MR Input Pulldown to go high. When logic LOW, the internal dividers and the outputs are en- abled. LVCMOS/LVTTL interface levels. Determines whether synthesizer is in PLL or bypass mode. LVCMOS/LVTTL 6 nPLL SEL Input Pulldown interface levels. 8V Power Analog supply pin. CCA F SEL0, 9, 11 Input Pulldown Frequency select pins. LVCMOS/LVTTL interface levels. F SEL1 10, 16 V Power Core supply pin. CC XTAL OUT, Parallel resonant crystal interface. XTAL OUT is the output, 12, 13 Input XTAL IN XTAL IN is the input. 14 REF CLK Input Pulldown LVCMOS/LVTTL reference clock input. Selects between crystal or REF CLK inputs as the the PLL Reference 15 nXTAL SEL Input Pulldown source. Selects XTAL inputs when LOW. Selects REF CLK when HIGH. LVCMOS/LVTTL interface levels. 17 V Power Negative supply pins. EE 18, 19 nQ1, Q1 Output Differential output pair. LVPECL interface levels. NOTE: Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values. TABLE 2. PIN CHARACTERISTICS Symbol Parameter Test Conditions Minimum Typical Maximum Units C Input Capacitance 4 pF IN R Input Pulldown Resistor 51 k PULLDOWN FEMTOCLOCKS CRYSTAL-TO- 2 REVISION A 2/20/15 3.3V, 2.5V LVPECL FREQUENCY SYNTHESIZER