175MHz, FemtoClock VCXO Based 843002I-40 Sonet/SDH Jitter Attenuators DATA SHEET General Description Features The ICS843002I-40 is a PLL based synchronous clock generator Two Differential LVPECL outputs that is optimized for SONET/SDH line card applications where Selectable CLKx, nCLKx differential input pairs jitter attenuation and frequency translation is needed. The device CLKx, nCLKx pairs can accept the following differential contains two internal PLL stages that are cascaded in series. The input levels: LVPECL, LVDS, LVHSTL, SSTL, HCSL or first PLL stage uses a VCXO which is optimized to provide single-ended LVCMOS or LVTTL levels reference clock jitter attenuation and to be jitter tolerant, and to provide a stable reference clock for the 2nd PLL stage (typically Maximum output frequency: 175MHz 19.44MHz). The second PLL stage provides additional frequency FemtoClock VCO frequency range: 560MHz - 700MHz multiplication (x32), and it maintains low output jitter by using a low phase noise FemtoClock VCO. PLL multiplication ratios are RMS phase jitter 155.52MHz, using a 19.44MHz crystal selected from internal lookup tables using device input selection (12kHz to 20MHz): 0.81ps (typical) pins. The device performance and the PLL multiplication ratios are Full 3.3V or mixed 3.3V core/2.5V output operating supply optimized to support non-FEC (non-Forward Error Correction) SONET/SDH applications with rates up to OC-48 (SONET) or -40C to 85C ambient operating temperature STM-16 (SDH). The VCXO requires the use of an external, Available in lead-free (RoHS 6) package inexpensive pullable crystal. VCXO PLL uses external passive loop filter components which are used to optimize the PLL loop bandwidth and damping characteristics for the given line card application. The ICS843002I-40 includes two clock input ports. Each one can accept either a single-ended or differential input. Each input port Pin Assignment also includes an activity detector circuit, which reports input clock activity through the LOR0 and LOR1 logic output pins. The two input ports feed an input selection mux. Hitless switching is accomplished through proper filter tuning. Jitter transfer and wander characteristics are influenced by loop filter tuning, and phase transient performance is influenced by both loop filter 32 31 30 29 28 27 26 25 tuning and alignment error between the two reference clocks. 1 24 LF1 LOR0 LF0 2 23 LOR1 Typical ICS843002I-40 configuration in SONET/SDH Systems: ISET 3 22 nc VCXO 19.44MHz crystal V 4 21 V CC CCO LVCMOS CLK0 5 20 V CCO LVPECL Input Reference clock frequency selections: nCLK0 nQB 6 19 19.44MHz, 38.88MHz, 77.76MHz, 155.52MHz, 311.04MHz, CLK SEL QB 7 18 622.08MHz nc V 8 17 EE Output clock frequency selections: 9 10 11 12 13 14 15 16 19.44MHz, 77.76MHz, 155.52MHz, Hi-Z ICS843002I-40 32-Lead VFQFN 5mm x 5mm x 0.925mm package body K Package Top View 843002I-40 Rev C 9/4/14 1 2014 Integrated Device Technology, Inc. QA SEL1 XTAL IN QA SEL0 XTAL OUT nc R SEL2 QB SEL1 R SEL1 R SEL0 QB SEL0 VCCA VEE QA CLK1 nQA nCLK1843002I-40 DATA SHEET Block Diagram 19.44 MHz External Pullable Loop xtal Components ISET ICS843002I-40 LF0 LF1 V Phase CCO LVCMOS Detector Charge R Divider = Divide Pump 1, 2, 4, 8, VCXO 19.44 MHz CLK1 by 32 and Loop Activity 16 or 32 1 Filter nCLK1 Detector LOR1 0 Divide by 32 CLK0 Activity nCLK0 Detector VCXO Jitter Attenuation PLL LOR0 V CCO LVPECL 622.08 MHz QA CLK SEL nQA 110 C0 Divider = FemtoClock 4, 8, 32, or HiZ PLL 111 110 2 x32 QA SEL1:0 111 QB C1 Divider = nQB 3 4, 8, 32, or HiZ R SEL2:0 2 QB SEL1:0 NOTE: 19.44MHz VCXO crystal shown is typical for SONET/SDH device applications. 175MHZ, FEMTOCLOCK VCXO BASED SONET/SDH JITTER 2 Rev C 9/4/14 ATTENUATORS XTAL IN XTAL OUT