Femtoclocks Crystal-to-3.3V 843004-01 Data Sheet LVPECL Frequency Synthesizer GENERAL DESCRIPTION FEATURES The 843004-01 is a 4 output LVPECL synthesizer optimized to Four 3.3V LVPECL outputs generate Ethernet reference clock frequencies and is a member Selectable crystal oscillator interface of the family of high performance clock solutions from IDT. Using or LVCMOS/LVTTL single-ended input a 25MHz 18pF parallel resonant crystal, the following frequencies can be generated based on the settings of 2 frequency select pins Supports the following output frequencies: (F SEL 1:0 ): 156.25MHz, 125MHz, 62.5MHz. The 843004-01 156.25MHz, 125MHz and 62.5MHz rd uses IDTs 3 generation low phase noise VCO technology and VCO range: 560MHz - 680MHz can achieve 1ps or lower typical rms phase jitter, easily meeting Ethernet jitter requirements. The 843004-01 is packaged in a small RMS phase jitter 156.25MHz, using a 25MHz crystal 24-pin TSSOP package. (1.875MHz - 20MHz): 0.57ps (typical) RMS phase noise at 156.25MHz (typical) Phase noise: Offset Noise Power 100Hz ................-95.5 dBc/Hz 1kHz .................-118 dBc/Hz 10kHz .................-126 dBc/Hz 100kHz ..............-126.6 dBc/Hz Full 3.3V supply mode -30C to 85C ambient operating temperature Available in lead-free RoHS compliant package FREQUENCY SELECT FUNCTION TABLE PIN ASSIGNMENT Inputs Output Frequency M Divider N Divider M/N nQ1 nQ2 1 24 (25MHz Ref.) F SEL1 F SEL0 Value Value Divider Value Q1 2 23 Q2 VCCo VCCO 3 22 0 0 25 4 6.25 156.25 Q0 4 Q3 21 0 1 25 5 5 125 nQ0 5 20 nQ3 MR 6 19 VEE 1 0 25 10 2.5 62.5 nPLL SEL 7 18 VCC 1 1 25 not used not used nc 8 nXTAL SEL 17 9 VCCA 16 TEST CLK 10 15 F SEL0 VEE BLOCK DIAGRAM 11 14 VCC XTAL IN 13 Pulldown 12 2 F SEL1 XTAL OUT F SEL 1:0 Pulldown 843004-01 nPLL SEL 24-Lead TSSOP Q0 F SEL 1:0 4.40mm x 7.8mm x 0.92mm Pulldown 0 0 4 nQO TEST CLK 11 package body 1 0 1 5 Q1 G Package 25MHz 1 0 10 VCO Top View XTAL IN 1 1 not used Phase nQ1 625MHz 0 OSC 0 Detector (w/25MHz XTAL OUT Reference) Pulldown Q2 nXTAL SEL nQ2 M = 25 (fixed) Q3 nQ3 Pulldown MR 2016 Integrated Device Technology, Inc 1 Revision B January 18, 2016843004-01 Data Sheet TABLE 1. PIN DESCRIPTIONS Number Name Type Description 1, 2 nQ1, Q1 Output Differential output pair. LVPECL interface levels. 3, 22 V Power Output supply pins. CCO 4, 5 Q0, nQ0 Ouput Differential output pair. LVPECL interface levels. Active HIGH Master Reset. When logic HIGH, the internal dividers are reset causing the true outputs Qx to go low and the inverted outputs nQx 6 MR Input Pulldown to go high. When logic LOW, the internal dividers and the outputs are enabled. LVCMOS/LVTTL interface levels. Selects between the PLL and TEST CLK as input to the dividers. When LOW, 7 nPLL SEL Input Pulldown selects PLL (PLL Enable). When HIGH, deselects the reference clock (PLL Bypass). LVCMOS/LVTTL interface levels. 8 nc Unused No connect. 9V Power Analog supply pin. CCA F SEL0, 10, 12 Input Pulldown Frequency select pins. LVCMOS/LVTTL interface levels. F SEL1 11, 18 V Power Core supply pin. CC XTAL OUT, Parallel resonant crystal interface. XTAL OUT is the output, 13, 14 Input XTAL IN XTAL IN is the input. 15, 19 V Power Negative supply pins. EE 16 TEST CLK Input Pulldown LVCMOS/LVTTL clock input. Selects between crystal or TEST CLK inputs as the the PLL Reference 17 nXTAL SEL Input Pulldown source. Selects XTAL inputs when LOW. Selects TEST CLK when HIGH. LVCMOS/LVTTL interface levels. 20, 21 nQ3, Q3 Output Differential output pair. LVPECL interface levels. 23, 24 Q2, nQ2 Output Differential output pair. LVPECL interface levels. NOTE: Pulldown refers to internal input resistors. See Table 2, Pin Characteristics, for typical values. TABLE 2. PIN CHARACTERISTICS Symbol Parameter Test Conditions Minimum Typical Maximum Units C Input Capacitance 4 pF IN R Input Pulldown Resistor 51 k PULLDOWN 2016 Integrated Device Technology, Inc 2 Revision B January 18, 2016