nXTAL SEL XTAL OUT FemtoClock Crystal-to-3.3V, 2.5V 843004I-01 LVPECL Frequency Synthesizer General Description Features The 843004I-01 is a 4 output LVPECL synthesizer optimized to Four 3.3V differential LVPECL output pairs generate Ethernet reference clock frequencies. Using a 25MHz Selectable crystal oscillator interface 18pF parallel resonant crystal, the following frequencies can be or LVCMOS/LVTTL single-ended clock input generated based on the settings of 2 frequency select pins Supports the following output frequencies: 156.25MHz, 125MHz, (F SEL 1:0 ): 156.25MHz, 125MHz, 62.5MHz. The 843004I-01 uses 62.5MHz rd IDTs 3 generation low phase noise VCO technology and can VCO range: 560MHz 680MHz achieve 1ps or lower typical rms phase jitter, easily meeting Ethernet RMS phase jitter 156.25MHz, using a 25MHz crystal jitter requirements. The 843004I-01 is packaged in a small 24-pin (1.875MHz 20MHz): 0.54ps (typical) TSSOP package. Full 3.3V or 2.5V supply modes -40C to 85C ambient operating temperature Lead-free (RoHS 6) package Frequency Select Function Table Inputs Output Frequency (MHz) F SEL1 F SEL0 M Div. Value N Div. Value M/N Div. Value (25MHz Reference) 0 0 25 4 6.25 156.25 01 25 5 5 125 1 0 25 10 2.5 62.5 1 1 25 Not Used Not Used Block Diagram Pin Assignment Pulldown 2 nQ2 F SEL 1:0 nQ1 1 24 Q1 2 23 Q2 Pulldown nPLL SEL V 3 22 VCCO CCO Q0 F SEL 1:0 Q0 4 21 Q3 nQ0 5 20 nQ3 Pulldown nQ0 0 0 4 TEST CLK 11 1 MR 6 19 VEE 0 1 5 Q1 nPLL SEL 7 18 VCC 1 0 10 VCO nc XTAL IN 8 17 1 1 not used nQ1 Phase 625MHz 9 V 16 TEST CLK 0 CCA OSC 0 Detector (w/25MHz F SEL0 10 15 VEE V XTAL OUT Reference) CC 11 14 XTAL IN F SEL1 12 13 Pulldown Q2 nXTAL SEL 843004I-01 nQ2 M = 25 (fixed) 24-Lead TSSOP Q3 4.4mm x 7.8mm x 0.925mm nQ3 package body Pulldown MR G Package Top View 2016 Integrated Device Technology, Inc 1 January 18, 2016843004I-01 Data Sheet Table 1. Pin Descriptions Number Name Type Description 1, 2 Output Differential output pair. LVPECL interface levels. nQ1, Q1 3, 22 V Power Output supply pins. CCO 4, 5 Output Differential output pair. LVPECL interface levels. Q0, nQ0 Active HIGH Master Reset. When logic HIGH, the internal dividers are reset causing the true outputs Qx to go low and the inverted outputs nQx to go high. When logic 6 MR Input Pulldown LOW, the internal dividers and the outputs are enabled. LVCMOS/LVTTL interface levels. Selects either the PLL or the active input reference to be routed to the output 7 nPLL SEL Input Pulldown dividers. When LOW, selects PLL (PLL Enable). When HIGH, selects the reference clock (PLL Bypass). LVCMOS/LVTTL interface levels. 8 Unused No connect. nc Power Analog supply pin. 9V CCA 10, F SEL0, Input Pulldown Frequency select pins. LVCMOS/LVTTL interface levels. 12 F SEL1 11, 18 V Power Core supply pins. CC 13, XTAL OUT, Input Parallel resonant crystal interface. XTAL OUT is the output, XTAL IN is the input. 14 XTAL IN 15, 19 V Power Negative supply pins. EE 16 TEST CLK Input Pulldown Single-ended clock input. LVCMOS/LVTTL interface levels. Selects between the single-ended TEST CLK or crystal interface as the PLL 17 nXTAL SEL Input Pulldown reference source. When HIGH, selects TEST CLK. When LOW, selects XTAL inputs. LVCMOS/LVTTL interface levels. 20, 21 Output Differential output pair. LVPECL interface levels. nQ3, Q3 23, 24 Output Differential output pair. LVPECL interface levels. Q2, nQ2 NOTE: Pulldown refers to internal input resistors. See Table 2, Pin Characteristics, for typical values. Table 2. Pin Characteristics Symbol Parameter Test Conditions Minimum Typical Maximum Units C Input Capacitance 4pF IN R Input Pulldown Resistor 51 k PULLDOWN 2016 Integrated Device Technology, Inc 2 January 18, 2016