843004AGI-156LF Renesas

nXTAL SEL XTAL OUT FemtoClock Crystal-to-3.3V, 2.5V LVPECL ICS843004I-156 Frequency Synthesizer DATA SHEET General Description Features The ICS843004I-156 is a four output LVPECL synthesizer optimized Four 3.3V differential LVPECL output pairs to generate Ethernet reference clock frequencies. Using a 25MHz Selectable crystal oscillator interface 18pF parallel resonant crystal, the ICS843004I-156 can generate or LVCMOS/LVTTL single-ended clock input 156.25MHz. 156.25MHz output frequency RD The ICS843004I-156 uses IDTs 3 generation low phase noise VCO range: 560MHz 680MHz VCO technology and can achieve 1ps or lower typical rms phase RMS phase jitter 156.25MHz, using a 25MHz crystal jitter, easily meeting Ethernet jitter requirements. The (1.875MHz 20MHz): 0.49ps (typical) ICS843004I-156 is packaged in a small 24-pin TSSOP E-Pad Full 3.3V or 2.5V supply modes package. -40C to 85C ambient operating temperature Available in lead-free (RoHS 6) package Block Diagram Pin Assignment Q0 nQ1 1 24 nQ2 Q1 2 23 Q2 Pulldown nQ0 nPLL SEL V 3 22 VCCO CCO Q0 4 21 Q3 Q1Q1 nQ0 5 20 nQ3 Pulldown REF CLK 11 MR 6 19 VEE 1 nQ1nQ1 nPLL SEL 7 18 VCC 25MHz VCO 4 nc 8 17 XTAL IN Phase 625MHz V 9 16 REF CLK CCA 0 OSC 0 Q2 Detector (w/25MHz nc 10 15 VEE XTAL OUT Reference) V 11 14 XTAL IN CC nQ2 nc 12 13 Pulldown nXTAL SEL Q3 ICS843004I-156 nQ3 M = 25 (fixed) 24-Lead TSSOP, E-Pad 4.4mm x 7.8mm x 0.925mm package body Pulldown MR G Package Top View ICS843004AGI-156 REVISION A FEBRUARY 27, 2013 1 2013 Integrated Device Technology, Inc. ICS843004I-156 Data Sheet FEMTOCLOCK CRYSTAL-TO-3.3V, 2.5V LVPECL FREQUENCY SYNTHESIZER Table 1. Pin Descriptions Number Name Type Description 1, 2 Output Differential output pair. LVPECL interface levels. nQ1, Q1 3, 22 V Power Output supply pins. CCO 4, 5 Output Differential output pair. LVPECL interface levels. Q0, nQ0 Active HIGH Master Reset. When logic HIGH, the internal dividers are reset causing the true outputs Qx to go low and the inverted outputs nQx to go 6 MR Input Pulldown high. When logic LOW, the internal dividers and the outputs are enabled. LVCMOS/LVTTL interface levels. Selects either the PLL or the active input reference to be routed to the 7 nPLL SEL Input Pulldown output dividers. When LOW, selects PLL (PLL Enable). When HIGH, selects the reference clock (PLL Bypass). LVCMOS/LVTTL interface levels. 8, 10,12 Unused No connect. nc Power Analog supply pin. 9V CCA Power Core supply pins. 11, 18 V CC 13, XTAL OUT, Parallel resonant crystal interface. XTAL OUT is the output, XTAL IN is Input 14 XTAL IN the input. 15, 19 V Power Negative supply pins. EE 16 REF CLK Input Pulldown Single-ended reference clock input. LVCMOS/LVTTL interface levels. Selects between the single-ended REF CLK or crystal interface as the PLL 17 nXTAL SEL Input Pulldown reference source. When HIGH, selects REF CLK. When LOW, selects XTAL inputs. LVCMOS/LVTTL interface levels. 20, 21 nQ3, Q3 Output Differential output pair. LVPECL interface levels. 23, 24 Output Differential output pair. LVPECL interface levels. Q2, nQ2 NOTE: Pulldown refers to internal input resistors. See Table 2, Pin Characteristics, for typical values. Table 2. Pin Characteristics Symbol Parameter Test Conditions Minimum Typical Maximum Units Input Capacitance 4 pF C IN R Input Pulldown Resistor 51 k PULLDOWN ICS843004AGI-156 REVISION A FEBRUARY 27, 2013 2 2013 Integrated Device Technology, Inc.