nXTAL SEL XTAL OUT FemtoClock LVCMOS/Crystal-to-3.3V, 843004I 2.5V LVPECL Frequency Synthesizer DATA SHEET General Description Features The 843004I is a 4 output LVPECL synthesizer optimized to generate Four 3.3V differential LVPECL output pairs Fibre Channel reference clock frequencies. Using a 26.5625MHz Selectable crystal oscillator interface or LVCMOS/LVTTL 18pF parallel resonant crystal, the following frequencies can be single-ended clock input generated based on the two frequency select pins (F SEL 1:0 ): Supports the following output frequencies: 212.5MHz, 187.5MHz, 212.5MHz, 187.5MHz, 159.375MHz, 156.25MHz, 106.25MHz, and 159.375MHz, 156.25MHz, 106.25MHz, 53.125MHz rd 53.125MHz. The 843004I uses IDTs 3 generation low phase noise VCO range: 560MHz 680MHz VCO technology and can achieve 1ps or lower typical rms phase Output skew: 50ps (maximum) jitter, easily meeting Fibre Channel jitter requirements. The 843004I is packaged in a small 24-pin TSSOP package. RMS phase jitter 212.5MHz, using a 26.5625MHz crystal (2.55MHz 20MHz): 0.47ps (typical) Full 3.3V or 2.5V supply modes -40C to 85C ambient operating temperature Available in lead-free (RoHS 6) package Bank A Frequency Table Inputs Input Frequency (MHz) F SEL1 F SEL0 M Div. Value N Div. Value M/N Div. Value Output Frequency (MHz) 26.5625 0 0 24 3 8 212.5 26.5625 0 1 24 4 6 159.375 26.5625 1 0 24 6 4 106.25 26.5625 1 1 24 12 2 53.125 26.04166 0 1 24 4 6 156.25 23.4375 0 0 24 3 8 187.5 Block Diagram Pin Assignment Pulldown 2 nQ2 F SEL 1:0 nQ1 1 24 2 23 Q2 Q1 Pulldown nPLL SEL Q0 VCCO V 3 22 CCO Q0 4 21 Q3 F SEL 1:0 nQ0 5 20 nQ3 Pulldown nQ0 0 0 3 TEST CLK 11 1 6 19 VEE MR 0 1 4 Q1 nPLL SEL 7 18 nc 26.5625MHz 1 0 6 nc VCO 8 17 XTAL IN nQ1 1 1 12 Phase 637.5MHz V 9 0 CCA 16 TEST CLK OSC 0 Detector (w/26.5625MHz F SEL0 VEE 10 15 Reference) XTAL OUT V CC 11 14 XTAL IN Q2 F SEL1 12 13 Pulldown nXTAL SEL nQ2 843004I M = 24 (fixed) Q3 24-Lead TSSOP 4.4mm x 7.8mm x 0.925mm nQ3 Pulldown package body MR G Package Top View 843004I Rev B 12/9/14 1 2014 Integrated Device Technology, Inc.843004I DATA SHEET Table 1. Pin Descriptions Number Name Type Description 1, 2 Output Differential output pair. LVPECL interface levels. nQ1, Q1 3, 22 V Power Output supply pins. CCO 4, 5 Output Differential output pair. LVPECL interface levels. Q0, nQ0 Active HIGH Master Reset. When logic HIGH, the internal dividers are reset causing the true outputs Qx to go low and the inverted outputs nQx to go high. 6 MR Input Pulldown When logic LOW, the internal dividers and the outputs are enabled. LVCMOS/LVTTL interface levels. Selects between the PLL and TEST CLK as input to the dividers. When LOW, 7 nPLL SEL Input Pulldown selects PLL (PLL Enable). When HIGH, deselects the reference clock (PLL Bypass). LVCMOS/LVTTL interface levels. 8, 18 Unused No connect. nc Power Analog supply pin. 9V CCA F SEL0, 10, 12 Input Pulldown Frequency select pins. LVCMOS/LVTTL interface levels. F SEL1 11 V Power Core supply pin. CC 13, XTAL OUT, Parallel resonant crystal interface. XTAL OUT is the output, XTAL IN is the Input 14 XTAL IN input. 15, 19 V Power Negative supply pins. EE 16 TEST CLK Input Pulldown Single-ended clock input. LVCMOS/LVTTL interface levels. Selects between the single-ended TEST CLK or crystal interface as the PLL 17 nXTAL SEL Input Pulldown reference source. When HIGH, selects TEST CLK. When LOW, selects XTAL. LVCMOS/LVTTL interface levels. 20, 21 Output Differential output pair. LVPECL interface levels. nQ3, Q3 23, 24 Output Differential output pair. LVPECL interface levels. Q2, nQ2 NOTE: Pulldown refers to internal input resistors. See Table 2, Pin Characteristics, for typical values. Table 2. Pin Characteristics Symbol Parameter Test Conditions Minimum Typical Maximum Units C Input Capacitance 4pF IN R Input Pulldown Resistor 51 k PULLDOWN Rev B 12/9/14 2 FEMTOCLOCK LVCMOS/CRYSTAL-TO-3.3V, 2.5V LVPECL FREQUENCY SYNTHESIZER